diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 15:59:51 +0100 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-20 18:59:44 +0000 |
commit | b274ccf59670c9110c75edbe563e6d5287d4604d (patch) | |
tree | 819ef70555d4eaaa49dc2633f09c78fd6b2d0099 /src/southbridge/amd/amd8111/nic.c | |
parent | f2e42c4a8ec75c162251c72df8ac3da12e8a3eb9 (diff) |
sb/amd/amd8111: Remove support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I5d7f3bfca47b86e4fd761f9462bc7297b487fdee
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36964
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/amd8111/nic.c')
-rw-r--r-- | src/southbridge/amd/amd8111/nic.c | 103 |
1 files changed, 0 insertions, 103 deletions
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c deleted file mode 100644 index a4abd0360a..0000000000 --- a/src/southbridge/amd/amd8111/nic.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/mmio.h> -#include <delay.h> -#include "amd8111.h" -#include "chip.h" - -#define CMD3 0x54 - -typedef enum { - VAL3 = (1 << 31), /* VAL bit for byte 3 */ - VAL2 = (1 << 23), /* VAL bit for byte 2 */ - VAL1 = (1 << 15), /* VAL bit for byte 1 */ - VAL0 = (1 << 7), /* VAL bit for byte 0 */ -}VAL_BITS; - -typedef enum { - /* VAL3 */ - ASF_INIT_DONE_ALIAS = (1 << 29), - /* VAL2 */ - JUMBO = (1 << 21), - VSIZE = (1 << 20), - VLONLY = (1 << 19), - VL_TAG_DEL = (1 << 18), - /* VAL1 */ - EN_PMGR = (1 << 14), - INTLEVEL = (1 << 13), - FORCE_FULL_DUPLEX = (1 << 12), - FORCE_LINK_STATUS = (1 << 11), - APEP = (1 << 10), - MPPLBA = (1 << 9), - /* VAL0 */ - RESET_PHY_PULSE = (1 << 2), - RESET_PHY = (1 << 1), - PHY_RST_POL = (1 << 0), -}CMD3_BITS; - -static void nic_init(struct device *dev) -{ - struct southbridge_amd_amd8111_config *conf; - struct resource *resource; - u8 *mmio; - - conf = dev->chip_info; - resource = find_resource(dev, PCI_BASE_ADDRESS_0); - mmio = res2mmio(resource, 0, 0); - - /* Hard Reset PHY */ - printk(BIOS_DEBUG, "Resetting PHY... "); - if (conf->phy_lowreset) { - write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); - } else { - write32((mmio + CMD3), VAL0 | RESET_PHY); - } - mdelay(15); - write32((mmio + CMD3), RESET_PHY); - printk(BIOS_DEBUG, "Done\n"); -} - -static void lpci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - pci_write_config32(dev, 0xc8, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, -}; - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, - .enable = amd8111_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_8111_NIC, -}; |