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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-11-23 18:03:46 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-04 16:39:33 +0000 |
| commit | 8cee45c3f8f05d936ba181f56405b8c936666a36 (patch) | |
| tree | 36e0cf79a1438e53b28ff51d0c6b5c9d7bd83cb8 /src/southbridge/amd/agesa/hudson/early_setup.c | |
| parent | 55009af42c39f413c49503670ce9bc2858974962 (diff) | |
sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/early_setup.c')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/early_setup.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c5e6c25b68..d85cb2b6f1 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -87,4 +87,22 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } +void hudson_lpc_decode(void) +{ + pci_devfn_t dev; + u32 tmp; + + dev = PCI_DEV(0, 0x14, 3); + /* Serial port numeration on Hudson: + * PORT0 - 0x3f8 + * PORT1 - 0x2f8 + * PORT5 - 0x2e8 + * PORT7 - 0x3e8 + */ + tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7; + + pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); +} + #endif /* _HUDSON_EARLY_SETUP_C_ */ |