From 8cee45c3f8f05d936ba181f56405b8c936666a36 Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Sat, 23 Nov 2019 18:03:46 +0100 Subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/hudson/early_setup.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/southbridge/amd/agesa/hudson/early_setup.c') diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c5e6c25b68..d85cb2b6f1 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -87,4 +87,22 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } +void hudson_lpc_decode(void) +{ + pci_devfn_t dev; + u32 tmp; + + dev = PCI_DEV(0, 0x14, 3); + /* Serial port numeration on Hudson: + * PORT0 - 0x3f8 + * PORT1 - 0x2f8 + * PORT5 - 0x2e8 + * PORT7 - 0x3e8 + */ + tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 + | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7; + + pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); +} + #endif /* _HUDSON_EARLY_SETUP_C_ */ -- cgit v1.2.3