diff options
| author | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2014-08-10 17:09:15 -0600 |
|---|---|---|
| committer | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2014-08-30 19:14:16 +0200 |
| commit | 1a59039c24cfe5c74a805064d3a360709ad16526 (patch) | |
| tree | 7860975252e93b6fe4dc7091b47ea5f16e9413ff /src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | |
| parent | b266c6b5448b17647946eb926b07920c28524a55 (diff) | |
AMD Steppe Eagle: New integrated southbridge (Avalon)
00730F01 contains the Avalon southbridge and a Platform Security
Processor (PSP). Supporting the PSP requires specific binaries to
be included in the ROM. The fletcher utility is used to sign PSP
binaries.
The IMC access routines are not accessible for newer AMD parts that
use pre-compiled AGESA. Change the Hudson code such that the IMC
code is not compiled if IMC is not selected in Kconfig.
Disable compilation of resume.c if HAVE_ACPI_RESUME is disabled.
The newer AMD mainboards will initially be released without ACPI
resume support (S3) due to the use of AGESA internals in the
existing Hudson routines. The Makefile change allows newer
mainboards to avoid the API issues.
Change Kconfig such that the FWM flag is always set for PSP-enabled
parts. This has the side effect of forcing the generation of the
FWM directory in the absence of GEC, IMC, and xHCI.
Change-Id: I6d056f54b60a64300841599490b9fafd561c4a7d
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6677
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 01f769c46d..f66547158d 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -29,6 +29,8 @@ #define FCH_INT_TABLE_SIZE 0x54 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON) +#define FCH_INT_TABLE_SIZE 0x63 #endif #define PIRQ_NC 0x1F /* Not Used */ @@ -73,6 +75,10 @@ #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON) +#define PIRQ_SD 0x17 /* SD */ +#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#endif #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define PIRQ_SD 0x42 /* SD 14h.7 */ #define PIRQ_GPP0 0x50 /* GPP INT 0 */ |