diff options
| author | zbao <fishbaozi@gmail.com> | 2015-07-02 16:53:09 -0400 |
|---|---|---|
| committer | Zheng Bao <zheng.bao@amd.com> | 2015-07-16 04:02:54 +0200 |
| commit | fe234c4d2a6ce0e1279597566336fe9277b8aa3b (patch) | |
| tree | 3dddf888d6d0f00afcbd048197b9fe76bba91a35 /src/soc | |
| parent | e731f721bedee7ce9c6ac21249fac05ff5cf63d3 (diff) | |
AMD Merlin Falcon: Mask bit 31 of BIST while doing BIST check
This is a result of the Silcon Observation. On warm reset, the BIST
is 0x80000000, which causes BIST error. We skip checking this bit.
The update will be in CZ BKDG 1.05.
The code is tested on AMD/bettong.
Change-Id: I51c3f3567f758766079f7c8789f1ff072e1a7c53
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/10902
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc')
0 files changed, 0 insertions, 0 deletions