diff options
| author | David Hendricks <dhendricks@fb.com> | 2018-04-13 15:11:43 -0700 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2018-04-16 05:57:06 +0000 |
| commit | f8d13d565819f975bfd6d4fb03fc04e6ecf198d2 (patch) | |
| tree | ab91015cb196424732afd11d2a76d28f9206303d /src/soc | |
| parent | 57d8ccb5f0c7733656ea2aeae4e2cc6feb998725 (diff) | |
intel/fsp_broadwell_de: Set FSP serial speed to match coreboot's
This makes FSP use the same baud rate as coreboot so that the user can
more easily change it without having to modify the FSP binary.
Change-Id: I0084aa9a0394ad7eabdd88809b66fc21a25ba316
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 7a9e8f5f55..0f9ffa9494 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -51,8 +51,20 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) /* * Serial Port */ - if (IS_ENABLED(CONFIG_INTEGRATED_UART)) + if (IS_ENABLED(CONFIG_INTEGRATED_UART)) { UpdData->SerialPortConfigure = 1; + /* values are from FSP .bsf file */ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_9600)) + UpdData->SerialPortBaudRate = 8; + else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_19200)) + UpdData->SerialPortBaudRate = 9; + else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_38400)) + UpdData->SerialPortBaudRate = 10; + else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_57600)) + UpdData->SerialPortBaudRate = 11; + else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_115200)) + UpdData->SerialPortBaudRate = 12; + } /* * Memory Down |