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authorRichard Spiegel <richard.spiegel@silverbackltd.com>2017-12-08 07:52:42 -0700
committerMartin Roth <martinroth@google.com>2017-12-14 03:51:03 +0000
commite89d444043b63529fa7d5a54e821ea491da006c2 (patch)
tree935f6cfaf43efc9a6f492941934f7ab8b1cf95ae /src/soc
parent1b75994b4e62d29f78517e50de6ea90d84aa08a6 (diff)
soc/amd/stoneyridge: Remove "\t" from name table
Remove "\t" from name strings in soc/amd/stoneyridge/southbridge.c array irq_association[], and change the print string in soc/amd/common/amd_pci_util.c that use the names from "%s" to "%-20s". This sets a fixed field of 20 characters for the string name, allowing for variable length to the names (up to 20 characters), thus saving memory space used by the strings. BUG=b:70344551 TEST=Build and boot, record output of irq routing and verify alignment. Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/common/block/pci/amd_pci_util.c4
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c72
2 files changed, 38 insertions, 38 deletions
diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c
index d30adf4134..c5659cbc79 100644
--- a/src/soc/amd/common/block/pci/amd_pci_util.c
+++ b/src/soc/amd/common/block/pci/amd_pci_util.c
@@ -70,7 +70,7 @@ void write_pci_int_table(void)
/* PIC IRQ routine */
printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for"
" PCI IRQ routing:\n"
- "\tPCI_INTR_INDEX\t\tPIC mode"
+ "PCI_INTR_INDEX\tname\t\t PIC mode"
"\tAPIC mode\n");
/*
* Iterate table idx_name, indexes outside the table are ignored
@@ -81,7 +81,7 @@ void write_pci_int_table(void)
for (i = 0 ; i < limit; i++) {
byte = idx_name[i].index;
write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]);
- printk(BIOS_DEBUG, "\t0x%02X %s\t0x%02X\t\t",
+ printk(BIOS_DEBUG, "0x%02X\t\t%-20s 0x%02X\t",
byte, idx_name[i].name,
read_pci_int_idx(byte, 0));
write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index ed1d10a591..a9081f87e0 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -40,46 +40,46 @@
* Order is not important.
*/
const static struct irq_idx_name irq_association[] = {
- { PIRQ_A, "INTA#\t" },
- { PIRQ_B, "INTB#\t" },
- { PIRQ_C, "INTC#\t" },
- { PIRQ_D, "INTD#\t" },
- { PIRQ_E, "INTE#\t" },
- { PIRQ_F, "INTF#\t" },
- { PIRQ_G, "INTG#\t" },
- { PIRQ_H, "INTH#\t" },
- { PIRQ_MISC, "Misc\t" },
- { PIRQ_MISC0, "Misc0\t" },
- { PIRQ_MISC1, "Misc1\t" },
- { PIRQ_MISC2, "Misc2\t" },
+ { PIRQ_A, "INTA#" },
+ { PIRQ_B, "INTB#" },
+ { PIRQ_C, "INTC#" },
+ { PIRQ_D, "INTD#" },
+ { PIRQ_E, "INTE#" },
+ { PIRQ_F, "INTF#" },
+ { PIRQ_G, "INTG#" },
+ { PIRQ_H, "INTH#" },
+ { PIRQ_MISC, "Misc" },
+ { PIRQ_MISC0, "Misc0" },
+ { PIRQ_MISC1, "Misc1" },
+ { PIRQ_MISC2, "Misc2" },
{ PIRQ_SIRQA, "Ser IRQ INTA" },
{ PIRQ_SIRQB, "Ser IRQ INTB" },
{ PIRQ_SIRQC, "Ser IRQ INTC" },
{ PIRQ_SIRQD, "Ser IRQ INTD" },
- { PIRQ_SCI, "SCI\t" },
- { PIRQ_SMBUS, "SMBUS\t" },
- { PIRQ_ASF, "ASF\t" },
- { PIRQ_HDA, "HDA\t" },
- { PIRQ_FC, "FC\t\t" },
- { PIRQ_PMON, "PerMon\t" },
- { PIRQ_SD, "SD\t\t" },
- { PIRQ_SDIO, "SDIO\t" },
- { PIRQ_IMC0, "IMC INT0\t" },
- { PIRQ_IMC1, "IMC INT1\t" },
- { PIRQ_IMC2, "IMC INT2\t" },
- { PIRQ_IMC3, "IMC INT3\t" },
- { PIRQ_IMC4, "IMC INT4\t" },
- { PIRQ_IMC5, "IMC INT5\t" },
- { PIRQ_EHCI, "EHCI\t" },
- { PIRQ_XHCI, "XHCI\t" },
- { PIRQ_SATA, "SATA\t" },
- { PIRQ_GPIO, "GPIO\t" },
- { PIRQ_I2C0, "I2C0\t" },
- { PIRQ_I2C1, "I2C1\t" },
- { PIRQ_I2C2, "I2C2\t" },
- { PIRQ_I2C3, "I2C3\t" },
- { PIRQ_UART0, "UART0\t" },
- { PIRQ_UART1, "UART1\t" },
+ { PIRQ_SCI, "SCI" },
+ { PIRQ_SMBUS, "SMBUS" },
+ { PIRQ_ASF, "ASF" },
+ { PIRQ_HDA, "HDA" },
+ { PIRQ_FC, "FC" },
+ { PIRQ_PMON, "PerMon" },
+ { PIRQ_SD, "SD" },
+ { PIRQ_SDIO, "SDIOt" },
+ { PIRQ_IMC0, "IMC INT0" },
+ { PIRQ_IMC1, "IMC INT1" },
+ { PIRQ_IMC2, "IMC INT2" },
+ { PIRQ_IMC3, "IMC INT3" },
+ { PIRQ_IMC4, "IMC INT4" },
+ { PIRQ_IMC5, "IMC INT5" },
+ { PIRQ_EHCI, "EHCI" },
+ { PIRQ_XHCI, "XHCI" },
+ { PIRQ_SATA, "SATA" },
+ { PIRQ_GPIO, "GPIO" },
+ { PIRQ_I2C0, "I2C0" },
+ { PIRQ_I2C1, "I2C1" },
+ { PIRQ_I2C2, "I2C2" },
+ { PIRQ_I2C3, "I2C3" },
+ { PIRQ_UART0, "UART0" },
+ { PIRQ_UART1, "UART1" },
};
/*