diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-12-24 12:54:11 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-28 09:34:34 +0000 |
| commit | db01d1e2fc097f3f54229b6db65fcf04026c01e4 (patch) | |
| tree | cec0edd3ce2eb63eda62f1237634bbe13be29b59 /src/soc | |
| parent | a0583a46b9b8373b2398565fc41f3602249ea8a5 (diff) | |
soc/mediatek/mt8186: Enable VRF12 software control for MT6366
PS8640 is a low power MIPI-to-eDP video format converter.
VRF12 does not provide power to PS8640 on krabby.
In original patch, VRF12 is not used, and is set to hardware control
for low power. We change the setting to remove hardware control.
Therefore, if we want to control VRF12 by software, we can control
it directly.
BUG=b:210806060
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I87d6a94b6fb343590d563ac1554ff87b11c01549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/mt8186/mt6366.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 450b783dcf..5cec47a04a 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -211,10 +211,6 @@ static struct pmic_setting lp_setting[] = { {0x1C1E, 0x1, 0x1, 2}, /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ {0x1C24, 0x0, 0x1, 2}, - /* [2:2]: RG_LDO_VRF12_HW1_OP_EN */ - {0x1C32, 0x1, 0x1, 2}, - /* [2:2]: RG_LDO_VRF12_HW1_OP_CFG */ - {0x1C38, 0x0, 0x1, 2}, /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ {0x1C46, 0x1, 0x1, 0}, /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ @@ -325,10 +321,6 @@ static struct pmic_setting lp_setting[] = { {0x1C1E, 0x1, 0x1, 2}, /* [2:2]: RG_LDO_VRF18_HW1_OP_CFG */ {0x1C24, 0x0, 0x1, 2}, - /* [2:2]: RG_LDO_VRF12_HW1_OP_EN */ - {0x1C32, 0x1, 0x1, 2}, - /* [2:2]: RG_LDO_VRF12_HW1_OP_CFG */ - {0x1C38, 0x0, 0x1, 2}, /* [0:0]: RG_LDO_VEFUSE_SW_OP_EN */ {0x1C46, 0x1, 0x1, 0}, /* [0:0]: RG_LDO_VCN33_SW_OP_EN */ |