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authorFelix Held <felix-coreboot@felixheld.de>2021-07-28 14:15:44 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-07-30 23:14:05 +0000
commitd828482c9b64d5bc7e99f756753fa197a740768b (patch)
treeec4f44d908f0bc184bbfd742f70396ea574ab392 /src/soc
parentc72df501a1f04df8ea6b03b97b7ddd0882c9ba19 (diff)
soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to table
GPIO bank 3 isn't used in coreboot, but the existence is documented in both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and for those two SoCs all 4 banks are covered by the corresponding Memory32Fixed region in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio_map.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
index 176dc2b9a6..ebfc0395e9 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
@@ -72,6 +72,8 @@
* +---------------------------------------------------------------------------+
* |0x1700 GPIO configuration registers bank 2 (following bank 1) |
* +---------------------------------------------------------------------------+
+ * |0x1800 GPIO configuration registers bank 3 (following bank 2) |
+ * +---------------------------------------------------------------------------+
* |0x1c00 xHCI Power Management registers |
* +---------------------------------------------------------------------------+
* |0x1d00 Wake device (AC DC timer) |