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authorFelix Held <felix-coreboot@felixheld.de>2023-06-05 15:30:10 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-06-06 17:28:50 +0000
commitd7ad1409b955f83e40da3b648e85bc3cc2b919a8 (patch)
tree1629742875a205780f8ec55136fdedaacdabc85f /src/soc
parentd0959dc800657efea4906ea5509a41ac3ca6d99a (diff)
soc/amd/stoneyridge/northbridge: reserve PCI config IO ports
This makes sure that the resource allocator won't use those ports for anything else. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I014ffe3ee94ec153e91113f9a17e89f24ca040b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75619 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/northbridge.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 75fdfa4a35..452a7bb2eb 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -334,6 +334,8 @@ void domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
+ fixed_io_range_reserved(dev, idx++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT);
+
/* 0x0 -> 0x9ffff */
ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);