diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-07-12 02:10:17 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-13 16:37:56 +0000 |
| commit | d19ebe0bd5c05badc7b800eab625559a8ac7d2f0 (patch) | |
| tree | 6984e986d03728e80e43a4da7ffec9263e4dde51 /src/soc | |
| parent | c7b27b3ad628f00ab4cd5cfae07d1796a7a25fb3 (diff) | |
soc/intel: Rename pcr.asl to pch_pcr.asl
The PCR (Private Configuration Register) is applicable to access the
P2SB register space starting with the Intel SkyLake generation of SoC.
Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside
the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in
SoC die (same as PCH die for U/H SoC) and another in IOE die.
This patch renames pcr.asl to pch_pcr.asl to reflect the actual source
of the P2SB IP in the die (i.e., SoC die or PCH die).
BUG=b:290856936
TEST=Able to build and boot google/rex.
Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/acpi/southbridge.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/acpi/pch_pcr.asl (renamed from src/soc/intel/common/acpi/pcr.asl) | 0 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/acpi/southbridge.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/acpi/southbridge.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/southbridge.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi/pch.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/southbridge.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/acpi/gpio.asl | 2 |
9 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index e663adc3c7..d14dd66990 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -6,7 +6,7 @@ #include <soc/pcr_ids.h> /* PCR access */ -#include <soc/intel/common/acpi/pcr.asl> +#include <soc/intel/common/acpi/pch_pcr.asl> /* PCH clock */ #include "camera_clock_ctl.asl" diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 052847d08c..20d4bfd897 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* PCR access */ -#include <soc/intel/common/acpi/pcr.asl> +#include <soc/intel/common/acpi/pch_pcr.asl> /* eMMC, SD Card */ #include "scs.asl" diff --git a/src/soc/intel/common/acpi/pcr.asl b/src/soc/intel/common/acpi/pch_pcr.asl index 2a940a3160..2a940a3160 100644 --- a/src/soc/intel/common/acpi/pcr.asl +++ b/src/soc/intel/common/acpi/pch_pcr.asl diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index 2da44bcb79..8b0748dc62 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -9,7 +9,7 @@ #include "pci_irqs.asl" /* PCR access */ -#include <soc/intel/common/acpi/pcr.asl> +#include <soc/intel/common/acpi/pch_pcr.asl> /* GPIO controller */ #include "gpio.asl" diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index 93e538edc3..a463304228 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -9,7 +9,7 @@ #include "pci_irqs.asl" /* PCR access */ -#include <soc/intel/common/acpi/pcr.asl> +#include <soc/intel/common/acpi/pch_pcr.asl> /* PCH clock */ #include "camera_clock_ctl.asl" diff --git a/src/soc/intel/meteorlake/acpi/southbridge.asl b/src/soc/intel/meteorlake/acpi/southbridge.asl index 6ecadbbd29..2d24fb2a54 100644 --- a/src/soc/intel/meteorlake/acpi/southbridge.asl +++ b/src/soc/intel/meteorlake/acpi/southbridge.asl @@ -6,7 +6,7 @@ #include <soc/pcr_ids.h> /* PCR access */ -#include <soc/intel/common/acpi/pcr.asl> +#include <soc/intel/common/acpi/pch_pcr.asl> /* PCH clock */ #include "camera_clock_ctl.asl" diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0aa8f95761..a2ab35c2da 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -27,7 +27,7 @@ #include "pcie.asl" /* PCR Access */ -#include <soc/intel/common/acpi/pcr.asl> +#include <soc/intel/common/acpi/pch_pcr.asl> /* PMC 0:1f.2 */ #include "pmc.asl" diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 83453e2633..c54bc675f2 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -6,7 +6,7 @@ #include <soc/pcr_ids.h> /* PCR access */ -#include <soc/intel/common/acpi/pcr.asl> +#include <soc/intel/common/acpi/pch_pcr.asl> /* PCH clock */ #include "camera_clock_ctl.asl" diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gpio.asl index ea00b03ee4..a67bdd7d5a 100644 --- a/src/soc/intel/xeon_sp/acpi/gpio.asl +++ b/src/soc/intel/xeon_sp/acpi/gpio.asl @@ -4,7 +4,7 @@ #include <soc/pcr_ids.h> #include <soc/irq.h> #include <soc/intel/common/block/acpi/acpi/gpio_op.asl> -#include <soc/intel/common/acpi/pcr.asl> +#include <soc/intel/common/acpi/pch_pcr.asl> Device (GPIO) { |