soc/intel: Use correct terminology for SPI flash operations

FPR is an attribute of the SPI flash component and not of the SPI bus
itself. Rename functions, file names and Kconfig option to make sure
this is conveyed correctly.

BUG=None
BRANCH=None
TEST=Compiles successfully.

Change-Id: I9f06f1a8ee28b8c56db64ddd6a19dd9179c54f50
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17560
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

9 files changed, 17 insertions, 12 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index cba2eab060..d1d660bc78 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -52,7 +52,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_LPSS_I2C
 	select SOC_INTEL_COMMON_SMI
-	select SOC_INTEL_COMMON_SPI_PROTECT
+	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
 	select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index 4da292ac85..eab3a12eac 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -22,7 +22,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <soc/intel/common/spi.h>
+#include <soc/intel/common/spi_flash.h>
 #include <soc/pci_devs.h>
 #include <soc/spi.h>
 #include <spi_flash.h>
@@ -420,7 +420,7 @@ int spi_read_status(uint8_t *status)
 	return 0;
 }
 
-int spi_get_fpr_info(struct fpr_info *info)
+int spi_flash_get_fpr_info(struct fpr_info *info)
 {
 	BOILERPLATE_CREATE_CTX(ctx);
 
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 5d8bf6664c..7ae7e60396 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -9,7 +9,7 @@ config CACHE_MRC_SETTINGS
 	bool "Save cached MRC settings"
 	default n
 
-config SOC_INTEL_COMMON_SPI_PROTECT
+config SOC_INTEL_COMMON_SPI_FLASH_PROTECT
 	bool
 	default n
 
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 38903a0ae7..d6e1e751d6 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -20,7 +20,7 @@ postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 ramstage-y += hda_verb.c
 ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
 ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_FLASH_PROTECT) += spi_flash.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
 ramstage-y += util.c
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c
index e44fb940b7..99a1fbfb15 100644
--- a/src/soc/intel/common/nvm.c
+++ b/src/soc/intel/common/nvm.c
@@ -22,7 +22,7 @@
 #include <spi_flash.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "nvm.h"
-#include "spi.h"
+#include "spi_flash.h"
 
 /* This module assumes the flash is memory mapped just below 4GiB in the
  * address space for reading. Also this module assumes an area it erased
diff --git a/src/soc/intel/common/spi.c b/src/soc/intel/common/spi_flash.c
index e73a55e125..c7717c9fe9 100644
--- a/src/soc/intel/common/spi.c
+++ b/src/soc/intel/common/spi_flash.c
@@ -15,7 +15,7 @@
 
 #include <arch/io.h>
 #include <console/console.h>
-#include "spi.h"
+#include "spi_flash.h"
 
 /*
  * Protect range of SPI flash defined by [start, start+size-1] using Flash
@@ -29,7 +29,7 @@ int spi_flash_protect(u32 start, u32 size)
 	int fpr;
 	uintptr_t fpr_base;
 
-	if (spi_get_fpr_info(&fpr_info) == -1) {
+	if (spi_flash_get_fpr_info(&fpr_info) == -1) {
 		printk(BIOS_ERR, "ERROR: FPR Info not found!\n");
 		return -1;
 	}
diff --git a/src/soc/intel/common/spi.h b/src/soc/intel/common/spi_flash.h
index a89f7925aa..d6bb079dbb 100644
--- a/src/soc/intel/common/spi.h
+++ b/src/soc/intel/common/spi_flash.h
@@ -13,6 +13,9 @@
  * GNU General Public License for more details.
  */
 
+#ifndef __INTEL_COMMON_SPI_FLASH_H__
+#define __INTEL_COMMON_SPI_FLASH_H__
+
 #define SPI_FPR_SHIFT		12
 #define SPI_FPR_MASK		0x7fff
 #define SPI_FPR_BASE_SHIFT	0
@@ -36,10 +39,12 @@ struct fpr_info {
  *
  * On success return 0 else -1.
  */
-int spi_get_fpr_info(struct fpr_info *info);
+int spi_flash_get_fpr_info(struct fpr_info *info);
 
 /*
  * Protect range of SPI flash defined by [start, start+size-1] using Flash
  * Protected Range (FPR) register if available.
  */
 int spi_flash_protect(u32 start, u32 size);
+
+#endif /* __INTEL_COMMON_SPI_FLASH_H__ */
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 04dbf0e1fb..988547c8a8 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -44,7 +44,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_LPSS_I2C
 	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_RESET
-	select SOC_INTEL_COMMON_SPI_PROTECT
+	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
 	select SMM_TSEG
 	select SMP
 	select SSE2
diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index eacd414046..cc6c20a4be 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -20,7 +20,7 @@
 #include <bootstate.h>
 #include <timer.h>
 #include <soc/flash_controller.h>
-#include <soc/intel/common/spi.h>
+#include <soc/intel/common/spi_flash.h>
 #include <soc/pci_devs.h>
 #include <soc/spi.h>
 #include <spi-generic.h>
@@ -384,7 +384,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
 	return slave;
 }
 
-int spi_get_fpr_info(struct fpr_info *info)
+int spi_flash_get_fpr_info(struct fpr_info *info)
 {
 	pch_spi_regs *spi_bar = get_spi_bar();