diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-11-28 13:58:57 +0100 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-11-30 21:53:21 +0000 |
| commit | cf9fc1ddfebffc76eaf86aae9ae8afbe9ab5925d (patch) | |
| tree | e2b3e2dd802f898e6ddabf047f79ea6a86b293fb /src/soc | |
| parent | c9c5e84d6fa68280e25d1f1a3d0f0454d39a55ad (diff) | |
soc/intel/fsp_baytrail: Rework acpi/cpu.asl
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/acpi.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/acpi/cpu.asl | 52 |
2 files changed, 15 insertions, 44 deletions
diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 2640a80daf..fb14af984c 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -524,6 +524,13 @@ void generate_cpu_entries(struct device *device) acpigen_pop_len(); } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(pattrs->num_cpus); } unsigned long acpi_madt_irq_overrides(unsigned long current) diff --git a/src/soc/intel/fsp_baytrail/acpi/cpu.asl b/src/soc/intel/fsp_baytrail/acpi/cpu.asl index dc26e0a7e6..5c153f4a59 100644 --- a/src/soc/intel/fsp_baytrail/acpi/cpu.asl +++ b/src/soc/intel/fsp_baytrail/acpi/cpu.asl @@ -14,59 +14,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +/* Notify OS to re-read CPU tables */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } + \_PR.CNOT (0x81) } -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +/* Notify OS to re-read CPU _PPC limit */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } + \_PR.CNOT (0x80) } -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +/* Notify OS to re-read Throttle Limit tables */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) - } Else { - Return (Package() {\_PR.CP00}) - } + \_PR.CNOT (0x82) } |