diff options
| author | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-11-10 00:35:02 +0100 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-03-07 12:47:01 +0000 |
| commit | c9b7d1fb57787d7037a5bce031a1300d13f5df40 (patch) | |
| tree | 57788b70b069229693dae5727cb8acc54eee3c14 /src/soc | |
| parent | 7a732b4781e7b83abda3230055d7110e1db730f3 (diff) | |
security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly.
* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.
Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc')
7 files changed, 24 insertions, 17 deletions
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 22226176e7..e4e3490395 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -35,7 +35,8 @@ SECTIONS PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) - VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K) + VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x33000, 2K) + VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) SRAM_END(BOOTROM_OFFSET + 0x80000) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 05042efb9f..cd81093fab 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -46,7 +46,8 @@ SECTIONS REGION(gram_bootblock, 0x1a000000, 28K, 1) ROMSTAGE(0x1a007000, 60K) VBOOT2_WORK(0x1a016000, 12K) - PRERAM_CBFS_CACHE(0x1a019000, 48K) + VBOOT2_TPM_LOG(0x1a019000, 2K) + PRERAM_CBFS_CACHE(0x1a019800, 46K) SRAM_END(0x1a066000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 5b92153142..adda86e11b 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -39,7 +39,8 @@ SECTIONS SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) - PRERAM_CBMEM_CONSOLE(0x00103000, 16K) + VBOOT2_TPM_LOG(0x00103000, 2K) + PRERAM_CBMEM_CONSOLE(0x00103800, 14K) WATCHDOG_TOMBSTONE(0x00107000, 4) PRERAM_CBFS_CACHE(0x00107004, 16K - 4) TIMESTAMP(0x0010B000, 4K) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index e01dd1c2ae..6a11a0ed8b 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -29,7 +29,8 @@ SECTIONS { SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) - PRERAM_CBMEM_CONSOLE(0x00103000, 16K) + VBOOT2_TPM_LOG(0x00103000, 2K) + PRERAM_CBMEM_CONSOLE(0x00103800, 14K) WATCHDOG_TOMBSTONE(0x00107000, 4) PRERAM_CBFS_CACHE(0x00107004, 16K - 4) TIMESTAMP(0x0010B000, 4K) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 615f05636d..40af0d5218 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -27,9 +27,10 @@ SECTIONS { SRAM_START(0x40000000) TTB(0x40000000, 16K + 32) - PRERAM_CBMEM_CONSOLE(0x40004020, 8K - 32) - PRERAM_CBFS_CACHE(0x40006000, 16K) - VBOOT2_WORK(0x4000A000, 16K) + PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) + PRERAM_CBFS_CACHE(0x40005800, 16K) + VBOOT2_WORK(0x40009800, 16K) + VBOOT2_TPM_LOG(0x4000D800, 2K) STACK(0x4000E000, 8K) BOOTBLOCK(0x40010000, 30K) VERSTAGE(0x40017800, 72K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index d807c06599..18171354d5 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -28,18 +28,19 @@ SECTIONS { SRAM_START(0x40000000) - PRERAM_CBMEM_CONSOLE(0x40000000, 4K) - PRERAM_CBFS_CACHE(0x40001000, 36K) - VBOOT2_WORK(0x4000A000, 12K) + PRERAM_CBMEM_CONSOLE(0x40000000, 2K) + PRERAM_CBFS_CACHE(0x40000800, 32K) + VBOOT2_WORK(0x40008800, 12K) + VBOOT2_TPM_LOG(0x4000B800, 2K) #if ENV_ARM64 - STACK(0x4000D000, 3K) + STACK(0x4000C000, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ - STACK(0x4000DC00, 3K) + STACK(0x4000CC00, 3K) #endif - TIMESTAMP(0x4000E800, 2K) - BOOTBLOCK(0x4000F000, 28K) - VERSTAGE(0x40016000, 64K) - ROMSTAGE(0x40026000, 104K) + TIMESTAMP(0x4000D800, 2K) + BOOTBLOCK(0x4000E000, 28K) + VERSTAGE(0x40015000, 66K) + ROMSTAGE(0x40025800, 106K) SRAM_END(0x40040000) DRAM_START(0x80000000) diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 4daf2b90bb..ab79594003 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -31,7 +31,8 @@ SECTIONS ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 80K) + PRERAM_CBFS_CACHE(0x205C000, 78K) + VBOOT2_TPM_LOG(0x206F800, 2K) VBOOT2_WORK(0x2070000, 16K) STACK(0x2074000, 16K) SRAM_END(0x2078000) |