diff options
| author | Julius Werner <jwerner@chromium.org> | 2024-06-03 17:39:01 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2024-06-05 20:31:03 +0000 |
| commit | c770ad624605d76b75bc70c15e69639b79691346 (patch) | |
| tree | e052c653dee98ee2318d38bd553edcd301788f15 /src/soc | |
| parent | 25e3c63b53cf640e1d7d3f9e2657555cd36745df (diff) | |
cpu/x86: Make 1GB paging the default
This patch flips the polarity of CONFIG_USE_1G_PAGES_TLB into
CONFIG_NEED_SMALL_2MB_PAGE_TABLES which is off by default, meaning
CPUs added in the future will automatically build the smaller 1GB pages.
We can expect support for this feature to be available on all future CPU
generations (with the possible exception of embedded edge cases), so
this default setting should make mistakes less likely and keep
maintenance effort lower. (Besides, enabling the support where it
doesn't work fails fast, whereas keeping it disabled where it could work
is an inefficiency that can easily go overlooked for a long time.)
While this is technically a CPU feature, not a northbridge feature, we
support a lot more individual CPUs than northbridges in the pre-SoC era,
and they tend to be closely coupled anyway. So select the option at the
northbridge level for older CPUs to keep things simpler.
Change-Id: I2cf1237a7fb63b8904c2a3d57fead162c66bacde
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/Kconfig | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 02b93c97ec..09fdbbaae4 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -33,6 +33,7 @@ config SOC_INTEL_BAYTRAIL select CPU_HAS_L2_ENABLE_MSR select TCO_SPACE_NOT_YET_SPLIT select USE_DDR3 + select NEED_SMALL_2MB_PAGE_TABLES help Bay Trail M/D part support. diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index d9bb481a1b..9b96d112fc 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -39,6 +39,7 @@ config SOC_INTEL_BRASWELL select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select NO_CBFS_MCACHE select TCO_SPACE_NOT_YET_SPLIT + select NEED_SMALL_2MB_PAGE_TABLES help Braswell M/D part support. diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index cb080f4ddc..9bee9becae 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -24,6 +24,7 @@ config SOC_INTEL_ELKHARTLAKE select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT + select NEED_SMALL_2MB_PAGE_TABLES select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_1 select PMC_GLOBAL_RESET_ENABLE_LOCK |