diff options
| author | Naresh Solanki <Naresh.Solanki@9elements.com> | 2023-05-24 10:29:45 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-28 20:11:25 +0000 |
| commit | c7338085feaba70d9f67d2dd797624cddae84e7c (patch) | |
| tree | 288f10b2352e7096b09ef3fd023610f8cdece9e9 /src/soc | |
| parent | 6230d4131881e9fa51d1099652605c890f93f53d (diff) | |
soc/intel/xeon_sp: Enable build for IO Margining
This commit enables the build for IO Margining, ensuring that ASPM is
disabled and certain FSP knobs are adjusted in coreboot as below
1. Enable DFXEnable
2. Disable PcieGlobalAspm
3. Disable KtiLinkL1En & KtiLinkL0pEn
Since the FSP UPD does not provide all the necessary knobs for IO
Margining, the following settings need to be applied during the FSP
build process:
1. Enable PcdBiosDfxKnobEnabled
2. Disable PchDmiAspm
3. Enable SataTestMode
4. Enable WmphyMargining
5. Disable IioErrorEn
TEST=Build for IBM sbp1 board.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 9 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 17 |
2 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 4db0529bc1..308ec2d45e 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -173,4 +173,13 @@ config INTEL_TXT_HEAP_SIZE endif # INTEL_TXT +config ENABLE_IO_MARGINING + bool "Enable IO Margining" + default n + depends on !PCIEXP_ASPM + help + Enable support for I/O margining. This is mutually exclusive with + ASPM. This option is intended for debugging and validation and + should normally be disabled. + endif diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index f36e5ccf1c..8f4e98eea4 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -200,6 +200,23 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) config_upd_from_vpd(mupd); initialize_iio_upd(mupd); mainboard_memory_init_params(mupd); + + if (CONFIG(ENABLE_IO_MARGINING)) { + printk(BIOS_INFO, "IO Margining Enabled.\n"); + /* Needed for IO Margining */ + mupd->FspmConfig.DFXEnable = 1; + + UPD_IIO_PCIE_PORT_CONFIG *iio_pcie_cfg; + int socket; + + iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; + + for (socket = 0; socket < MAX_SOCKET; socket++) + iio_pcie_cfg[socket].PcieGlobalAspm = 0; + + mupd->FspmConfig.KtiLinkL1En = 0; + mupd->FspmConfig.KtiLinkL0pEn = 0; + } } static uint8_t get_error_correction_type(const uint8_t RasModesEnabled) |