spi: Clean up SPI flash driver interface

RW flag was added to spi_slave structure to get around a requirement on
some AMD flash controllers that need to group together all spi volatile
operations (write/erase). This rw flag is not a property or attribute of
the SPI slave or controller. Thus, instead of saving it in spi_slave
structure, clean up the SPI flash driver interface. This allows
chipsets/mainboards (that require volatile operations to be grouped) to
indicate beginning and end of such grouped operations.

New user APIs are added to allow users to perform probe, read, write,
erase, volatile group begin and end operations. Callbacks defined in
spi_flash structure are expected to be used only by the SPI flash
driver. Any chipset that requires grouping of volatile operations can
select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and
define callbacks for chipset_volatile_group_{begin,end}.

spi_claim_bus/spi_release_bus calls have been removed from the SPI flash
chip drivers which end up calling do_spi_flash_cmd since it already has
required calls for claiming and releasing SPI bus before performing a
read/write operation.

BUG=None
BRANCH=None
TEST=Compiles successfully.

Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17462
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

17 files changed, 63 insertions, 72 deletions

diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c
index f38607cf5b..87dd66fd59 100644
--- a/src/soc/imgtec/pistachio/spi.c
+++ b/src/soc/imgtec/pistachio/spi.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <console/console.h>
 #include <soc/cpu.h>
 #include <soc/spi.h>
 #include <spi_flash.h>
@@ -444,7 +445,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
 	img_slave->base = base;
 	slave->bus = bus;
 	slave->cs = cs;
-	slave->rw = SPI_READ_FLAG | SPI_WRITE_FLAG;
 	slave->max_transfer_size = IMGTEC_SPI_MAX_TRANSFER_SIZE;
 
 	device_parameters->bitrate = 64;
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index d60176a9aa..018572cfab 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -19,12 +19,14 @@
 
 #include <arch/early_variables.h>
 #include <arch/io.h>
+#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <soc/intel/common/spi.h>
 #include <soc/pci_devs.h>
 #include <soc/spi.h>
 #include <spi_flash.h>
+#include <spi-generic.h>
 #include <stdlib.h>
 #include <string.h>
 
@@ -224,7 +226,8 @@ void spi_release_bus(struct spi_slave *slave)
 	/* No magic needed here. */
 }
 
-static int nuclear_spi_erase(struct spi_flash *flash, uint32_t offset, size_t len)
+static int nuclear_spi_erase(const struct spi_flash *flash, uint32_t offset,
+			     size_t len)
 {
 	int ret;
 	size_t erase_size;
@@ -274,7 +277,8 @@ static size_t get_xfer_len(uint32_t addr, size_t len)
 	return xfer_len;
 }
 
-static int nuclear_spi_read(struct spi_flash *flash, uint32_t addr, size_t len, void *buf)
+static int nuclear_spi_read(const struct spi_flash *flash, uint32_t addr,
+			size_t len, void *buf)
 {
 	int ret;
 	size_t xfer_len;
@@ -300,8 +304,8 @@ static int nuclear_spi_read(struct spi_flash *flash, uint32_t addr, size_t len,
 	return SUCCESS;
 }
 
-static int nuclear_spi_write(struct spi_flash *flash,
-			   uint32_t addr, size_t len, const void *buf)
+static int nuclear_spi_write(const struct spi_flash *flash, uint32_t addr,
+			size_t len, const void *buf)
 {
 	int ret;
 	size_t xfer_len;
@@ -326,7 +330,7 @@ static int nuclear_spi_write(struct spi_flash *flash,
 	return SUCCESS;
 }
 
-static int nuclear_spi_status(struct spi_flash *flash, uint8_t *reg)
+static int nuclear_spi_status(const struct spi_flash *flash, uint8_t *reg)
 {
 	int ret;
 	BOILERPLATE_CREATE_CTX(ctx);
@@ -379,10 +383,10 @@ static struct spi_flash *nuclear_flash_probe(struct spi_slave *spi)
 	 * flash->status_cmd = ???
 	 */
 
-	flash->write = nuclear_spi_write;
-	flash->erase = nuclear_spi_erase;
-	flash->read = nuclear_spi_read;
-	flash->status = nuclear_spi_status;
+	flash->internal_write = nuclear_spi_write;
+	flash->internal_erase = nuclear_spi_erase;
+	flash->internal_read = nuclear_spi_read;
+	flash->internal_status = nuclear_spi_status;
 
 	return flash;
 }
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index ffe619866f..d651350cd5 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -21,7 +21,7 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_ids.h>
-#include <spi_flash.h>
+#include <spi-generic.h>
 
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index 01fe773dea..97ca2e56ef 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -22,7 +22,7 @@
 #include <rules.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
-#include <spi_flash.h>
+#include <spi-generic.h>
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c
index 6b86faf2e8..e44fb940b7 100644
--- a/src/soc/intel/common/nvm.c
+++ b/src/soc/intel/common/nvm.c
@@ -81,7 +81,7 @@ int nvm_erase(void *start, size_t size)
 {
 	if (nvm_init() < 0)
 		return -1;
-	return flash->erase(flash, nvm_mmio_to_flash_offset(start), size);
+	return spi_flash_erase(flash, nvm_mmio_to_flash_offset(start), size);
 }
 
 /* Write data to NVM. Returns 0 on success < 0 on error.  */
@@ -89,7 +89,8 @@ int nvm_write(void *start, const void *data, size_t size)
 {
 	if (nvm_init() < 0)
 		return -1;
-	return flash->write(flash, nvm_mmio_to_flash_offset(start), size, data);
+	return spi_flash_write(flash, nvm_mmio_to_flash_offset(start), size,
+				data);
 }
 
 /* Read flash status register to determine if write protect is active */
@@ -107,7 +108,7 @@ int nvm_is_write_protected(void)
 		wp_gpio = get_write_protect_state();
 
 		/* Read Status Register 1 */
-		if (flash->status(flash, &sr1) < 0) {
+		if (spi_flash_status(flash, &sr1) < 0) {
 			printk(BIOS_ERR,
 				"Failed to read SPI status register 1\n");
 			return -1;
diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c
index ed0d12165b..6f2fdbbd6a 100644
--- a/src/soc/intel/fsp_baytrail/nvm.c
+++ b/src/soc/intel/fsp_baytrail/nvm.c
@@ -67,7 +67,7 @@ int nvm_erase(void *start, size_t size)
 {
 	if (nvm_init() < 0)
 		return -1;
-	flash->erase(flash, to_flash_offset(start), size);
+	spi_flash_erase(flash, to_flash_offset(start), size);
 	return 0;
 }
 
@@ -76,6 +76,6 @@ int nvm_write(void *start, const void *data, size_t size)
 {
 	if (nvm_init() < 0)
 		return -1;
-	flash->write(flash, to_flash_offset(start), size, data);
+	spi_flash_write(flash, to_flash_offset(start), size, data);
 	return 0;
 }
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 374e7f6a44..b021175961 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -22,7 +22,7 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_ids.h>
-#include <spi_flash.h>
+#include <spi-generic.h>
 
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index 56c7c69527..5a715a4011 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -18,12 +18,12 @@
 #include <stdlib.h>
 #include <string.h>
 #include <bootstate.h>
-#include <spi_flash.h>
 #include <timer.h>
 #include <soc/flash_controller.h>
 #include <soc/intel/common/spi.h>
 #include <soc/pci_devs.h>
 #include <soc/spi.h>
+#include <spi-generic.h>
 
 static inline uint16_t spi_read_hsfs(pch_spi_regs * const regs)
 {
@@ -181,7 +181,7 @@ void spi_release_bus(struct spi_slave *slave)
 	/* Handled by PCH automatically. */
 }
 
-int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
+int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len)
 {
 	u32 start, end, erase_size;
 	int ret = 0;
@@ -192,8 +192,6 @@ int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
 		return -1;
 	}
 
-	flash->spi->rw = SPI_WRITE_FLAG;
-
 	start = offset;
 	end = start + len;
 
@@ -231,7 +229,8 @@ static void pch_read_data(uint8_t *data, int len)
 	}
 }
 
-int pch_hwseq_read(struct spi_flash *flash, u32 addr, size_t len, void *buf)
+int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
+		void *buf)
 {
 	uint8_t block_len;
 
@@ -292,8 +291,8 @@ static void pch_fill_data(const uint8_t *data, int len)
 		writel_(temp32, (uint8_t *)spi_bar->fdata + (i - (i % 4)));
 }
 
-int pch_hwseq_write(struct spi_flash *flash,
-			   u32 addr, size_t len, const void *buf)
+int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
+		const void *buf)
 {
 	uint8_t block_len;
 	uint32_t start = addr;
@@ -330,7 +329,7 @@ int pch_hwseq_write(struct spi_flash *flash,
 	return 0;
 }
 
-int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg)
+int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg)
 {
 	size_t block_len = SPI_READ_STATUS_LENGTH;
 	const int timeout_ms = 6;
@@ -358,10 +357,10 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi)
 	flash->spi = spi;
 	flash->name = "Opaque HW-sequencing";
 
-	flash->write = pch_hwseq_write;
-	flash->erase = pch_hwseq_erase;
-	flash->read = pch_hwseq_read;
-	flash->status = pch_hwseq_read_status;
+	flash->internal_write = pch_hwseq_write;
+	flash->internal_erase = pch_hwseq_erase;
+	flash->internal_read = pch_hwseq_read;
+	flash->internal_status = pch_hwseq_read_status;
 
 	/* The hardware sequencing supports 4KiB or 64KiB erase. Use 4KiB. */
 	flash->sector_size = 4*KiB;
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
index 49d60b0cd4..00500670fe 100644
--- a/src/soc/intel/skylake/include/soc/flash_controller.h
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -21,13 +21,12 @@
 #include <console/console.h>
 #include <spi_flash.h>
 
-int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len);
-int pch_hwseq_write(struct spi_flash *flash,
-			   u32 addr, size_t len, const void *buf);
-
-int pch_hwseq_read(struct spi_flash *flash,
-			  u32 addr, size_t len, void *buf);
-int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg);
+int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len);
+int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
+		const void *buf);
+int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
+		void *buf);
+int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg);
 
 
 #if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c
index db69cbeab7..16224046d7 100644
--- a/src/soc/intel/skylake/romstage/spi.c
+++ b/src/soc/intel/skylake/romstage/spi.c
@@ -16,6 +16,7 @@
 
 #include <soc/flash_controller.h>
 #include <soc/romstage.h>
+#include <spi-generic.h>
 
 /*
  * Minimal set of commands to read WPSR from SPI.
diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c
index 5d73f3aba2..dc64d4083c 100644
--- a/src/soc/mediatek/mt8173/flash_controller.c
+++ b/src/soc/mediatek/mt8173/flash_controller.c
@@ -157,7 +157,8 @@ static int pio_read(u32 addr, u8 *buf, u32 len)
 	return 0;
 }
 
-static int nor_read(struct spi_flash *flash, u32 addr, size_t len, void *buf)
+static int nor_read(const struct spi_flash *flash, u32 addr, size_t len,
+		void *buf)
 {
 	u32 next;
 
@@ -195,8 +196,8 @@ static int nor_read(struct spi_flash *flash, u32 addr, size_t len, void *buf)
 	return 0;
 }
 
-static int nor_write(struct spi_flash *flash, u32 addr, size_t len,
-		       const void *buf)
+static int nor_write(const struct spi_flash *flash, u32 addr, size_t len,
+		const void *buf)
 {
 	const u8 *buffer = (const u8 *)buf;
 
@@ -214,7 +215,7 @@ static int nor_write(struct spi_flash *flash, u32 addr, size_t len,
 	return 0;
 }
 
-static int nor_erase(struct spi_flash *flash, u32 offset, size_t len)
+static int nor_erase(const struct spi_flash *flash, u32 offset, size_t len)
 {
 	int sector_start = offset;
 	int sector_num = (u32)len / flash->sector_size;
@@ -242,10 +243,10 @@ struct spi_flash *mt8173_nor_flash_probe(struct spi_slave *spi)
 	write32(&mt8173_nor->wrprot, SFLASH_COMMAND_ENABLE);
 	flash.spi = spi;
 	flash.name = "mt8173 flash controller";
-	flash.write = nor_write;
-	flash.erase = nor_erase;
-	flash.read = nor_read;
-	flash.status = 0;
+	flash.internal_write = nor_write;
+	flash.internal_erase = nor_erase;
+	flash.internal_read = nor_read;
+	flash.internal_status = 0;
 	flash.sector_size = 0x1000;
 	flash.erase_cmd = SECTOR_ERASE_CMD;
 	flash.size = CONFIG_ROM_SIZE;
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/spi.h b/src/soc/qualcomm/ipq40xx/include/soc/spi.h
index 014b333667..1fd6a571ca 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/spi.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/spi.h
@@ -32,9 +32,9 @@
 #ifndef _IPQ40XX_SPI_H_
 #define _IPQ40XX_SPI_H_
 
-#include <spi_flash.h>
 #include <soc/iomap.h>
 #include <soc/qup.h>
+#include <spi-generic.h>
 
 #define BLSP0_QUP_REG_BASE		((void *)0x78b5000u)
 #define BLSP1_QUP_REG_BASE		((void *)0x78b6000u)
diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c
index 8d39f77ae4..dcd00c0065 100644
--- a/src/soc/qualcomm/ipq40xx/spi.c
+++ b/src/soc/qualcomm/ipq40xx/spi.c
@@ -28,6 +28,7 @@
  */
 
 #include <arch/io.h>
+#include <console/console.h>
 #include <delay.h>
 #include <gpio.h>
 #include <soc/iomap.h>
diff --git a/src/soc/qualcomm/ipq806x/include/soc/spi.h b/src/soc/qualcomm/ipq806x/include/soc/spi.h
index 3e623463cc..4f6f055e61 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/spi.h
+++ b/src/soc/qualcomm/ipq806x/include/soc/spi.h
@@ -6,7 +6,7 @@
 #ifndef _IPQ806X_SPI_H_
 #define _IPQ806X_SPI_H_
 
-#include <spi_flash.h>
+#include <spi-generic.h>
 #include <soc/iomap.h>
 
 #define QUP5_BASE	((uint32_t)GSBI_QUP5_BASE)
diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c
index 4a353130e1..71a8c29085 100644
--- a/src/soc/qualcomm/ipq806x/spi.c
+++ b/src/soc/qualcomm/ipq806x/spi.c
@@ -3,6 +3,7 @@
  */
 
 #include <arch/io.h>
+#include <console/console.h>
 #include <delay.h>
 #include <gpio.h>
 #include <soc/iomap.h>
diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c
index 57e9ca117e..3666de39d1 100644
--- a/src/soc/rockchip/common/spi.c
+++ b/src/soc/rockchip/common/spi.c
@@ -37,45 +37,30 @@ struct rockchip_spi_slave {
 
 static struct rockchip_spi_slave rockchip_spi_slaves[] = {
 	{
-	 .slave = {
-		   .bus = 0,
-		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
-		   },
+	 .slave = { .bus = 0, },
 	 .regs = (void *)SPI0_BASE,
 	},
 	{
-	 .slave = {.bus = 1, .rw = SPI_READ_FLAG,},
+	 .slave = { .bus = 1, },
 	 .regs = (void *)SPI1_BASE,
 	},
 	{
-	 .slave = {
-		   .bus = 2,
-		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
-		   },
+	 .slave = { .bus = 2, },
 	 .regs = (void *)SPI2_BASE,
 	},
 #ifdef SPI3_BASE
 	{
-	 .slave = {
-		   .bus = 3,
-		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
-		   },
+	 .slave = { .bus = 3, },
 	 .regs = (void *)SPI3_BASE,
 	},
 #ifdef SPI4_BASE
 	{
-	 .slave = {
-		   .bus = 4,
-		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
-		   },
+	 .slave = { .bus = 4, },
 	 .regs = (void *)SPI4_BASE,
 	},
 #ifdef SPI5_BASE
 	{
-	 .slave = {
-		   .bus = 5,
-		   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
-		   },
+	 .slave = { .bus = 5, },
 	 .regs = (void *)SPI5_BASE,
 	},
 #endif
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index 589809d5af..fd31a2fdf7 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -19,7 +19,7 @@
 #include <console/console.h>
 #include <soc/cpu.h>
 #include <soc/spi.h>
-#include <spi_flash.h>
+#include <spi-generic.h>
 #include <stdlib.h>
 #include <string.h>
 #include <symbols.h>
@@ -48,13 +48,12 @@ static struct exynos_spi_slave exynos_spi_slaves[3] = {
 	},
 	// SPI 1
 	{
-		.slave = { .bus = 1, .rw = SPI_READ_FLAG, },
+		.slave = { .bus = 1, },
 		.regs = (void *)EXYNOS5_SPI1_BASE,
 	},
 	// SPI 2
 	{
-		.slave = { .bus = 2,
-			   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, },
+		.slave = { .bus = 2, },
 		.regs = (void *)EXYNOS5_SPI2_BASE,
 	},
 };