summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2020-11-12 20:41:57 +0100
committerArthur Heymans <arthur@aheymans.xyz>2020-11-20 10:13:31 +0000
commita8798a317983508385138bb39f41e5e614e957f6 (patch)
tree666bd2fe52dda1d5c4e73f41d7a2bbabb0c92aa3 /src/soc
parent7ba970aa78816dd29052cd34304b6ea67953c003 (diff)
soc/intel/common/p2sb: Add helper function to determine p2sb state
Change-Id: I1d6f9c18160806e289e98c2fa5d290c61434112f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47530 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/p2sb/p2sb.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index d97cd8d2d4..9673a2cf71 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -15,6 +15,18 @@
#define HIDE_BIT (1 << 0)
+static bool p2sb_is_hidden(void)
+{
+ const uint16_t pci_vid = pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID);
+
+ if (pci_vid == 0xffff)
+ return true;
+ if (pci_vid == PCI_VENDOR_ID_INTEL)
+ return false;
+ printk(BIOS_ERR, "P2SB PCI_VENDOR_ID is invalid, unknown if hidden\n");
+ return true;
+}
+
void p2sb_enable_bar(void)
{
/* Enable PCR Base address in PCH */
@@ -59,8 +71,7 @@ void p2sb_unhide(void)
{
p2sb_set_hide_bit(0);
- if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) !=
- PCI_VENDOR_ID_INTEL)
+ if (p2sb_is_hidden())
die_with_post_code(POST_HW_INIT_FAILURE,
"Unable to unhide PCH_DEV_P2SB device !\n");
}
@@ -69,8 +80,7 @@ void p2sb_hide(void)
{
p2sb_set_hide_bit(1);
- if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) !=
- 0xFFFF)
+ if (!p2sb_is_hidden())
die_with_post_code(POST_HW_INIT_FAILURE,
"Unable to hide PCH_DEV_P2SB device !\n");
}