diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 02:14:51 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 00:44:44 +0000 |
| commit | a6f02a8c494a6a8584caf0453a028d76bdd2d972 (patch) | |
| tree | 0521c51dc3dd3154100fb425b4ed4bc3aafc0831 /src/soc | |
| parent | d79b87a1d6fcd6228edbd894e7e7ebc9b85d2813 (diff) | |
soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
Commit 360684b (soc/intel/common: add TCC activation functionality) made
Broadwell use common SoC code. However, this makes Broadwell depend on
SoC code, which prevents splitting Broadwell into CPU, northbridge and
southbridge, a stepping stone before merging with Haswell and Lynxpoint.
Tested on out-of-tree Acer E5-573, still boots.
Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46731
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 00460c6282..694c7277a4 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -290,6 +290,28 @@ static void configure_c_states(void) wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } +static void configure_thermal_target(void) +{ + config_t *conf; + struct device *lapic; + msr_t msr; + + /* Find pointer to CPU configuration */ + lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + if (!lapic || !lapic->chip_info) + return; + conf = lapic->chip_info; + + /* Set TCC activation offset if supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } +} + static void configure_misc(void) { msr_t msr; @@ -372,7 +394,7 @@ static void cpu_core_init(struct device *cpu) configure_misc(); /* Thermal throttle activation offset */ - configure_tcc_thermal_target(); + configure_thermal_target(); /* Enable Direct Cache Access */ configure_dca_cap(); |