diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2016-12-22 13:48:46 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-26 17:36:33 +0100 |
| commit | 9d2f3de48c3f9fbca0124b2f851e6057e2f43a1b (patch) | |
| tree | 43183b51a989896b55d1cc9f40a350336cc3c0f5 /src/soc | |
| parent | c2973d196d1224a1253478dc29d5f8fa004eaab8 (diff) | |
soc/intel/skylake: set TCC activation by BSP only
TCC activation functionality has package scope. It was set
for all CPU in the system which is unnecessary.
In this patch TCC activation is being set by the BSP only.
BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built for skylake platform and verified the TCC activation
value before and after S3.
Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3ec8d2c702..e8616f08c4 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -197,7 +197,7 @@ static void configure_thermal_target(void) config_t *conf = dev->chip_info; msr_t msr; - /* Set TCC activaiton offset if supported */ + /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); @@ -366,9 +366,6 @@ static void cpu_core_init(device_t cpu) /* Configure Intel Speed Shift */ configure_isst(); - /* Thermal throttle activation offset */ - configure_thermal_target(); - /* Enable Direct Cache Access */ configure_dca_cap(); @@ -484,6 +481,9 @@ void soc_init_cpus(device_t dev) if (mp_init_with_smm(cpu_bus, &mp_ops)) { printk(BIOS_ERR, "MP initialization failure.\n"); } + + /* Thermal throttle activation offset */ + configure_thermal_target(); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) |