diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2020-08-27 11:44:38 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-08-28 14:20:30 +0000 |
| commit | 913ea9278f50b73427a50a54e91f8d5502d93219 (patch) | |
| tree | e33acaae2444dcb9825306bb1c60a50e6c073e92 /src/soc | |
| parent | 2afee1299176c643854941e49d74506e1d98fed3 (diff) | |
util/gen_spd: translate DeviceBusWidth to die bus width
If a memory part is a x16 part that has two dies and only a single
rank, then the x16 describes the part width (since this solution will
need to be a stacked solution) and as such, we must translate the
DeviceBusWidth to the "die bus width" instead.
Change DeviceBusWidth variable name to PackageBusWidth to be more
descriptive
BUG=b:166645306, b:160157545
TEST=run gen_spd and verify that spds for parts matching description
above changed appropriately.
Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/tigerlake/spd/ddr4-spd-2.hex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/spd/ddr4-spd-2.hex b/src/soc/intel/tigerlake/spd/ddr4-spd-2.hex index 15e4d3fcf1..85b203599b 100644 --- a/src/soc/intel/tigerlake/spd/ddr4-spd-2.hex +++ b/src/soc/intel/tigerlake/spd/ddr4-spd-2.hex @@ -1,4 +1,4 @@ -23 11 0C 03 85 21 91 08 00 00 00 00 02 03 00 00 +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A 20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |