util: Add spd_tools to generate DDR4 SPDs for TGL boards

Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.

In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for DDR4
memory used in memory down configurations on Intel Tiger Lake (TGL)
based platforms. These tools generate SPDs following JESD79-4C and
Jedec "4.1.2.L-5 R29 v103" specification.

Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
  part list provided by the mainboard in JSON format. Additionally,
  generates a SPD manifest file (in CSV format) with information about
  what memory part from the global list uses which of the generated
  SPD files.

* gen_part_id.go: Allocates DRAM strap IDs for different DDR4
  memory parts used by the board. Takes as input list of memory parts
  used by the board (with one memory part on each line) and the SPD
  manifest file generated by gen_spd.go. Generates Makefile.inc for
  integrating the generated SPD files in the coreboot build.

BUG=b:160157545

Change-Id: I263f936b332520753a6791c8d892fc148cb6f103
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

3 files changed, 67 insertions, 0 deletions

diff --git a/src/soc/intel/tigerlake/spd/ddr4/ddr4-spd-1.hex b/src/soc/intel/tigerlake/spd/ddr4/ddr4-spd-1.hex
new file mode 100644
index 0000000000..32d141f21f
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/ddr4/ddr4-spd-1.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00
+00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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diff --git a/src/soc/intel/tigerlake/spd/ddr4/ddr4-spd-2.hex b/src/soc/intel/tigerlake/spd/ddr4/ddr4-spd-2.hex
new file mode 100644
index 0000000000..15e4d3fcf1
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/ddr4/ddr4-spd-2.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 85 21 91 08 00 00 00 00 02 03 00 00
+00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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diff --git a/src/soc/intel/tigerlake/spd/ddr4/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4/spd_manifest.generated.txt
new file mode 100644
index 0000000000..22fce5c302
--- /dev/null
+++ b/src/soc/intel/tigerlake/spd/ddr4/spd_manifest.generated.txt
@@ -0,0 +1,3 @@
+H5AN8G6NDJR-XNC,ddr4-spd-1.hex
+MT40A512M16TB-062E:J,ddr4-spd-1.hex
+H5ANAG6NCMR-XNC,ddr4-spd-2.hex