diff options
| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-11-18 20:03:22 -0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2021-11-24 11:19:40 +0000 |
| commit | 8e0bfe263c1a944f230b38097a5a917b77542afe (patch) | |
| tree | 0d3b918407749cac6e06170f7776f9acfff23611 /src/soc | |
| parent | 7aedf83b30abdd045a10fb5da091b130c04234dd (diff) | |
soc/intel/elkhartlake: Disable Intel PSE by default
Disable PSE loading by default. If left enabled (current default),
the EHL coreboot will end up in endless restart loop, due to FSP
unable to locate PSE FW image and trigger global reset.
However disabling this flag (PchPseEnable) will cause the coreboot
to trigger a single reset due to CSE signal (HECI: CSE does not
meet required prerequisites). The reason behind this is that FSP
need to perform static disabling (power gate) to fully shut down
PSE HW, and to do this will need to global reset entire system
including CSE. Then PMC will power gate PSE from the start.
To avoid this behavior, the best way to disable PSE is to disable
via IFWI FIT softstrap (For specific detail can refer to Intel EHL
coreboot MR2 release notes). With this, PMC will power gate PSE
from the first cold boot and system will boot happily without
single reset behavior.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/elkhartlake/romstage/fsp_params.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index a15b030dd3..ecb6304945 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -123,6 +123,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, config->ibecc.region_mask); } } + /* PSE (Intel Programmable Services Engine) switch */ + m_cfg->PchPseEnable = 0; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |