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authorAaron Durbin <adurbin@chromium.org>2015-08-04 14:04:47 -0500
committerAaron Durbin <adurbin@chromium.org>2015-08-14 15:15:20 +0200
commit85654a66504f2c87f129d3c414995be4b6cdc09f (patch)
treeeb65761f5881029a2877a909aab140f6f95aba03 /src/soc
parentc5b91d6800872268c9f92b13465bf3769d3631e1 (diff)
skylake: set DISB in GEN_PMCON_A register properly
DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM training is complete. However, as a 8-bit write was being performed the bit was never being set. BUG=chrome-os-partner:43516 BRANCH=None TEST=Built and booted to kernel. Rebooted. Noted full memory training was not being peformed. Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290337 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11183 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/pmc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index b62a28886b..a97f7517fa 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -47,7 +47,7 @@ static const struct reg_script pch_pmc_misc_init_script[] = {
/* Enable SCI and clear SLP requests. */
REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
/* Indicate DRAM init done for MRC */
- REG_PCI_OR8(GEN_PMCON_A, DISB),
+ REG_PCI_OR32(GEN_PMCON_A, DISB),
REG_SCRIPT_END
};