soc/intel/apollolake: Change PCI macros to match Skylake

Change PCI macros in such a way they can be transparently used across
romstage and ramstage.

Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15483
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

2 files changed, 92 insertions, 67 deletions

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 044ef913b9..b2afc4a72f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -134,49 +134,49 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
 	case XDCI_DEVFN:
 		silconfig->UsbOtg = 0;
 		break;
-	case I2C0_DEVFN:
+	case LPSS_DEVFN_I2C0:
 		silconfig->I2c0Enable = 0;
 		break;
-	case I2C1_DEVFN:
+	case LPSS_DEVFN_I2C1:
 		silconfig->I2c1Enable = 0;
 		break;
-	case I2C2_DEVFN:
+	case LPSS_DEVFN_I2C2:
 		silconfig->I2c2Enable = 0;
 		break;
-	case I2C3_DEVFN:
+	case LPSS_DEVFN_I2C3:
 		silconfig->I2c3Enable = 0;
 		break;
-	case I2C4_DEVFN:
+	case LPSS_DEVFN_I2C4:
 		silconfig->I2c4Enable = 0;
 		break;
-	case I2C5_DEVFN:
+	case LPSS_DEVFN_I2C5:
 		silconfig->I2c5Enable = 0;
 		break;
-	case I2C6_DEVFN:
+	case LPSS_DEVFN_I2C6:
 		silconfig->I2c6Enable = 0;
 		break;
-	case I2C7_DEVFN:
+	case LPSS_DEVFN_I2C7:
 		silconfig->I2c7Enable = 0;
 		break;
-	case UART0_DEVFN:
+	case LPSS_DEVFN_UART0:
 		silconfig->Hsuart0Enable = 0;
 		break;
-	case UART1_DEVFN:
+	case LPSS_DEVFN_UART1:
 		silconfig->Hsuart1Enable = 0;
 		break;
-	case UART2_DEVFN:
+	case LPSS_DEVFN_UART2:
 		silconfig->Hsuart2Enable = 0;
 		break;
-	case UART3_DEVFN:
+	case LPSS_DEVFN_UART3:
 		silconfig->Hsuart3Enable = 0;
 		break;
-	case SPI0_DEVFN:
+	case LPSS_DEVFN_SPI0:
 		silconfig->Spi0Enable = 0;
 		break;
-	case SPI1_DEVFN:
+	case LPSS_DEVFN_SPI1:
 		silconfig->Spi1Enable = 0;
 		break;
-	case SPI2_DEVFN:
+	case LPSS_DEVFN_SPI2:
 		silconfig->Spi2Enable = 0;
 		break;
 	case SDCARD_DEVFN:
@@ -201,7 +201,7 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
 
 static void parse_devicetree(struct FSP_S_CONFIG *silconfig)
 {
-	struct device *dev = dev_find_slot(0, NB_DEVFN);
+	struct device *dev = NB_DEV_ROOT;
 
 	if (!dev) {
 		printk(BIOS_ERR, "Could not find root device\n");
@@ -222,7 +222,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 	/* Load VBT before devicetree-specific config. */
 	silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
 
-	struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN);
+	struct device *dev = NB_DEV_ROOT;
+
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
 		return;
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index fc046d13ab..88a7a070dd 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -17,63 +17,87 @@
 
 #include <rules.h>
 
-#define _LPSS_PCI_DEVFN(slot, func)		PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
+#define _LPSS_PCI_DEVFN(slot, func)	PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
+#define _PCI_DEVFN(slot, func)		PCI_DEVFN(slot, func)
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
 #include <device/pci_def.h>
-#define _LPSS_PCI_DEV(slot, func)		dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
+#define _LPSS_PCI_DEV(slot, func)	dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
+#define _PCI_DEV(slot, func)		dev_find_slot(0, PCI_DEVFN(slot, func))
 #else
 #include <arch/io.h>
-#define _LPSS_PCI_DEV(slot, func)		PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
+#define _LPSS_PCI_DEV(slot, func)	PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
+#define _PCI_DEV(slot, func)		PCI_DEV(0, slot, func)
 #endif
 
+#define NB_DEVFN			_PCI_DEVFN(0, 0)
+#define NB_DEV_ROOT			_PCI_DEV(0x0, 0)
+
+#define P2SB_DEV			_PCI_DEV(0xd, 0)
+#define PMC_DEV				_PCI_DEV(0xd, 1)
+#define SPI_DEV				_PCI_DEV(0xd, 2)
+
+#define ISH_DEV				_PCI_DEV(0x11, 0)
+#define ISH_DEVFN			_PCI_DEVFN(0x11, 0)
+
+#define SATA_DEV			_PCI_DEV(0x12, 0)
+#define SATA_DEVFN			_PCI_DEVFN(0x12, 0)
+
+#define PCIEA0_DEVFN			_PCI_DEVFN(0x13, 0)
+#define PCIEA1_DEVFN			_PCI_DEVFN(0x13, 1)
+#define PCIEA2_DEVFN			_PCI_DEVFN(0x13, 2)
+#define PCIEA3_DEVFN			_PCI_DEVFN(0x13, 3)
+#define PCIEB0_DEVFN			_PCI_DEVFN(0x14, 0)
+#define PCIEB1_DEVFN			_PCI_DEVFN(0x14, 1)
+
+#define XHCI_DEV			_PCI_DEV(0x15, 0)
+#define XHCI_DEVFN			_PCI_DEVFN(0x15, 0)
+
+#define XDCI_DEV			_PCI_DEV(0x15, 1)
+#define XDCI_DEVFN			_PCI_DEVFN(0x15, 1)
+
+/* LPSS I2C, 2 devices cover 8 controllers */
+#define LPSS_DEV_SLOT_I2C_D0		0x16
+#define  LPSS_DEVFN_I2C0		_LPSS_PCI_DEVFN(I2C_D0, 0)
+#define  LPSS_DEVFN_I2C1		_LPSS_PCI_DEVFN(I2C_D0, 1)
+#define  LPSS_DEVFN_I2C2		_LPSS_PCI_DEVFN(I2C_D0, 2)
+#define  LPSS_DEVFN_I2C3		_LPSS_PCI_DEVFN(I2C_D0, 3)
+#define LPSS_DEV_SLOT_I2C_D1		0x17
+#define  LPSS_DEVFN_I2C4		_LPSS_PCI_DEVFN(I2C_D1, 0)
+#define  LPSS_DEVFN_I2C5		_LPSS_PCI_DEVFN(I2C_D1, 1)
+#define  LPSS_DEVFN_I2C6		_LPSS_PCI_DEVFN(I2C_D1, 2)
+#define  LPSS_DEVFN_I2C7		_LPSS_PCI_DEVFN(I2C_D1, 3)
+
 /* LPSS UART */
-#define LPSS_DEV_SLOT_UART	0x18
-#define  LPSS_DEVFN_UART0	_LPSS_PCI_DEVFN(UART, 0)
-#define  LPSS_DEVFN_UART1	_LPSS_PCI_DEVFN(UART, 1)
-#define  LPSS_DEVFN_UART2	_LPSS_PCI_DEVFN(UART, 2)
-#define  LPSS_DEVFN_UART3	_LPSS_PCI_DEVFN(UART, 3)
-#define  LPSS_DEV_UART0		_LPSS_PCI_DEV(UART, 0)
-#define  LPSS_DEV_UART1		_LPSS_PCI_DEV(UART, 1)
-#define  LPSS_DEV_UART2		_LPSS_PCI_DEV(UART, 2)
-#define  LPSS_DEV_UART3		_LPSS_PCI_DEV(UART, 3)
-
-#define NB_BUS			0
-#define NB_DEVFN		PCI_DEVFN(0, 0)
-#define NB_DEV_ROOT		PCI_DEV(NB_BUS, 0x0, 0)
-#define P2SB_DEV		PCI_DEV(0, 0xd, 0)
-#define PMC_DEV			PCI_DEV(0, 0xd, 1)
-#define SPI_DEV			PCI_DEV(0, 0xd, 2)
-#define LPC_DEV			PCI_DEV(0, 0x1f, 0)
-
-#define ISH_DEVFN		PCI_DEVFN(0x11, 0)
-#define SATA_DEVFN		PCI_DEVFN(0x12, 0)
-#define PCIEA0_DEVFN		PCI_DEVFN(0x13, 0)
-#define PCIEA1_DEVFN		PCI_DEVFN(0x13, 1)
-#define PCIEA2_DEVFN		PCI_DEVFN(0x13, 2)
-#define PCIEA3_DEVFN		PCI_DEVFN(0x13, 3)
-#define PCIEB0_DEVFN		PCI_DEVFN(0x14, 0)
-#define PCIEB1_DEVFN		PCI_DEVFN(0x14, 1)
-#define XHCI_DEVFN		PCI_DEVFN(0x15, 0)
-#define XDCI_DEVFN		PCI_DEVFN(0x15, 1)
-#define I2C0_DEVFN		PCI_DEVFN(0x16, 0)
-#define I2C1_DEVFN		PCI_DEVFN(0x16, 1)
-#define I2C2_DEVFN		PCI_DEVFN(0x16, 2)
-#define I2C3_DEVFN		PCI_DEVFN(0x16, 3)
-#define I2C4_DEVFN		PCI_DEVFN(0x17, 0)
-#define I2C5_DEVFN		PCI_DEVFN(0x17, 1)
-#define I2C6_DEVFN		PCI_DEVFN(0x17, 2)
-#define I2C7_DEVFN		PCI_DEVFN(0x17, 3)
-#define UART0_DEVFN		PCI_DEVFN(0x18, 0)
-#define UART1_DEVFN		PCI_DEVFN(0x18, 1)
-#define UART2_DEVFN		PCI_DEVFN(0x18, 2)
-#define UART3_DEVFN		PCI_DEVFN(0x18, 3)
-#define SPI0_DEVFN		PCI_DEVFN(0x19, 0)
-#define SPI1_DEVFN		PCI_DEVFN(0x19, 1)
-#define SPI2_DEVFN		PCI_DEVFN(0x19, 2)
-#define SDCARD_DEVFN		PCI_DEVFN(0x1b, 0)
-#define EMMC_DEVFN		PCI_DEVFN(0x1c, 0)
-#define SDIO_DEVFN		PCI_DEVFN(0x1e, 0)
-#define SMBUS_DEVFN		PCI_DEVFN(0x1f, 1)
+#define LPSS_DEV_SLOT_UART		0x18
+#define  LPSS_DEVFN_UART0		_LPSS_PCI_DEVFN(UART, 0)
+#define  LPSS_DEVFN_UART1		_LPSS_PCI_DEVFN(UART, 1)
+#define  LPSS_DEVFN_UART2		_LPSS_PCI_DEVFN(UART, 2)
+#define  LPSS_DEVFN_UART3		_LPSS_PCI_DEVFN(UART, 3)
+#define  LPSS_DEV_UART0			_LPSS_PCI_DEV(UART, 0)
+#define  LPSS_DEV_UART1			_LPSS_PCI_DEV(UART, 1)
+#define  LPSS_DEV_UART2			_LPSS_PCI_DEV(UART, 2)
+#define  LPSS_DEV_UART3			_LPSS_PCI_DEV(UART, 3)
+
+/* LPSS SPI */
+#define LPSS_DEV_SLOT_SPI		0x19
+#define  LPSS_DEVFN_SPI0		_LPSS_PCI_DEVFN(SPI, 0)
+#define  LPSS_DEVFN_SPI1		_LPSS_PCI_DEVFN(SPI, 1)
+#define  LPSS_DEVFN_SPI2		_LPSS_PCI_DEVFN(SPI, 2)
+
+#define SDCARD_DEV			_PCI_DEV(0x1b, 0)
+#define SDCARD_DEVFN			_PCI_DEVFN(0x1b, 0)
+
+#define EMMC_DEV			_PCI_DEV(0x1c, 0)
+#define EMMC_DEVFN			_PCI_DEVFN(0x1c, 0)
+
+#define SDIO_DEV			_PCI_DEV(0x1e, 0)
+#define SDIO_DEVFN			_PCI_DEVFN(0x1e, 0)
+
+#define LPC_DEV				_PCI_DEV(0x1f, 0)
+#define LPC_DEVFN			_PCI_DEVFN(0x1f, 0)
+
+#define SMBUS_DEV			_PCI_DEV(0x1f, 1)
+#define SMBUS_DEVFN			_PCI_DEVFN(0x1f, 1)
 #endif