diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-21 21:21:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-21 11:22:59 +0000 |
| commit | 7608ea0c9f6c8763bd80628adf2d977e60823275 (patch) | |
| tree | d9dfab540638a69c1b2498075f88e8479af5c1fa /src/soc | |
| parent | b192af12e3e483699f2e75790b2eb6e79b5b4f71 (diff) | |
soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver
commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.
BUG=b:169934025
TEST=BERT table that gets generated in a follow-up patch for Picasso
points to expected BERT region and Linux is able to access, decode and
display it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/memmap.c | 18 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fsp_m_params.c | 1 |
3 files changed, 3 insertions, 17 deletions
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 5dd3056f0c..bd80e78249 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -91,7 +91,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; - mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); mcfg->serial_port_baudrate = get_uart_baudrate(); diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 6ec437cb1d..c4a9643c11 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -62,19 +62,7 @@ void smm_region(uintptr_t *start, size_t *size) void bert_reserved_region(void **start, size_t *size) { - struct range_entry bert; - int status; - - *start = NULL; - *size = 0; - - status = fsp_find_range_hob(&bert, AMD_FSP_BERT_HOB_GUID.b); - - if (status < 0) { - printk(BIOS_ERR, "Error: unable to find BERT HOB\n"); - return; - } - - *start = (void *)(uintptr_t)range_entry_base(&bert); - *size = range_entry_size(&bert); + *start = cbmem_top(); + *size = CONFIG_ACPI_BERT_SIZE; + printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%lx\n", *start, *size); } diff --git a/src/soc/amd/picasso/fsp_m_params.c b/src/soc/amd/picasso/fsp_m_params.c index 28803b32c3..f196e48f12 100644 --- a/src/soc/amd/picasso/fsp_m_params.c +++ b/src/soc/amd/picasso/fsp_m_params.c @@ -68,7 +68,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; - mcfg->bert_size = CONFIG_ACPI_BERT_SIZE; mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM); mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1; |