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authorSubrata Banik <subrata.banik@intel.com>2020-12-19 19:36:45 +0530
committerHung-Te Lin <hungte@chromium.org>2020-12-23 03:29:00 +0000
commit683c95e4ab460f349a31379700fb5672991a2722 (patch)
tree0836701420530a912489ee7f758b811c897e3794 /src/soc
parent65f5932e0cb48ce333e4e0625a7740f8f9ce1ddf (diff)
soc/intel/alderlake: Enable support for extended BIOS window
Port commit ba75c4c (soc/intel/tigerlake: Enable support for extended BIOS window) for Alderlake Change-Id: Iaa8464d45884de433cca4f6a250cdd8d4c8f3661 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/alderlake/Kconfig7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 7e693cb373..a77acc3e1f 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
select FSP_COMPRESS_FSP_S_LZ4
+ select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB
@@ -96,6 +97,12 @@ config CHIPSET_DEVICETREE
string
default "soc/intel/alderlake/chipset.cb"
+config EXT_BIOS_WIN_BASE
+ default 0xf8000000
+
+config EXT_BIOS_WIN_SIZE
+ default 0x2000000
+
config IFD_CHIPSET
string
default "adl"