diff options
| author | Yu-Ping Wu <yupingso@chromium.org> | 2021-03-02 17:52:08 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-08 03:17:19 +0000 |
| commit | 656fa56a227445957d95b3cfcb46ea4fd8d238d1 (patch) | |
| tree | 282f3d174b0caf8cda69b646c6c6bc925c957b0b /src/soc | |
| parent | a3b19441f6956c09e175973899f92f8774090582 (diff) | |
soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 400K
Move PRERAM_CBMEM_CONSOLE to SRAM L2C and increase its size from 15K to
400K. With this change, most part of the DRAM full calibration log can
be stored in CBMEM console.
BUG=b:181933863
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=none
Change-Id: I896884d298e197149f75865e9d00579124a34404
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/memlayout.ld | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 2624d82c55..e84383ba44 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -26,7 +26,6 @@ SECTIONS TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) WATCHDOG_TOMBSTONE(0x00104000, 4) - PRERAM_CBMEM_CONSOLE(0x00104004, 15K - 4) CBFS_MCACHE(0x00107c00, 8K) TIMESTAMP(0x00109c00, 1K) STACK(0x0010a000, 12K) @@ -49,6 +48,7 @@ SECTIONS */ DRAM_INIT_CODE(0x00250000, 256K) PRERAM_CBFS_CACHE(0x00290000, 48K) + PRERAM_CBMEM_CONSOLE(0x0029c000, 400K) SRAM_L2C_END(0x00300000) DRAM_START(0x40000000) |