soc/intel/alderlake: Avoid reprogramming the SRAM BAR

This patch avoids the redundant programming of SRAM BAR when
the SRAM PCI device is enabled. Rather read the PCH SRAM Base
Address Register while enabling crashlog feature.

Additionally, this patch relies on PCI enumeration to get the
SRAM BAR rather than hijacking the SPI temporary base address
which might have resulted in problems if SPI is disabled on
some platform with BAR being implemented.

TEST=Able to build and boot google/marasov and crashlog is working.

Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

1 files changed, 31 insertions, 5 deletions

diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c
index b47d5644f9..5a08c25a62 100644
--- a/src/soc/intel/alderlake/crashlog.c
+++ b/src/soc/intel/alderlake/crashlog.c
@@ -28,6 +28,31 @@ u32 __weak cl_get_cpu_mb_int_addr(void)
 	return CRASHLOG_MAILBOX_INTF_ADDRESS;
 }
 
+/* Get the SRAM BAR. */
+static uintptr_t sram_get_bar(void)
+{
+	uintptr_t sram_bar;
+	const struct device *dev;
+	struct resource *res;
+
+	dev = pcidev_path_on_root(PCH_DEVFN_SRAM);
+	if (!dev) {
+		printk(BIOS_ERR, "PCH_DEVFN_SRAM device not found!\n");
+		return 0;
+	}
+
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!res) {
+		printk(BIOS_ERR, "PCH SRAM device not found!\n");
+		return 0;
+	}
+
+	/* Get the base address of the resource */
+	sram_bar = res->base;
+
+	return sram_bar;
+}
+
 bool pmc_cl_discovery(void)
 {
 	u32 tmp_bar_addr = 0, desc_table_addr = 0;
@@ -58,10 +83,11 @@ bool pmc_cl_discovery(void)
 	}
 	m_pmc_crashLog_support = true;
 
-	/* Program BAR 0 and enable command register memory space decoding */
-	tmp_bar_addr = SPI_BASE_ADDRESS;
-	pci_write_config32(PCH_DEV_SRAM, PCI_BASE_ADDRESS_0, tmp_bar_addr);
-	pci_or_config16(PCH_DEV_SRAM, PCI_COMMAND, PCI_COMMAND_MEMORY);
+	tmp_bar_addr = sram_get_bar();
+	if (tmp_bar_addr == 0) {
+		printk(BIOS_ERR, "PCH SRAM not available, crashlog feature can't be enabled.\n");
+		return false;
+	}
 
 	if (discovery_buf.bits.discov_mechanism == 1) {
 		/* discovery mode */
@@ -113,7 +139,7 @@ u32 cl_get_cpu_bar_addr(void)
 
 u32 cl_get_cpu_tmp_bar(void)
 {
-	return SPI_BASE_ADDRESS;
+	return sram_get_bar();
 }
 
 bool  cl_pmc_sram_has_mmio_access(void)