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authorRaul E Rangel <rrangel@chromium.org>2021-02-05 17:29:12 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-02-10 19:01:22 +0000
commit5461662c6626898947aca193011761c9530c71d0 (patch)
tree39525836cb27c53d19fcc868f166eb40ed742051 /src/soc
parent466edb51b4b0c19486f14f43bee8d6834c52abc9 (diff)
soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI
Required so we pass SPI information down to depthcharge. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/cezanne/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index a881ef802d..530b4e7992 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -13,6 +13,7 @@ config SOC_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
+ select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select FSP_COMPRESS_FSP_M_LZMA
select FSP_COMPRESS_FSP_S_LZMA
select HAVE_CF9_RESET
@@ -30,6 +31,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
+ select SOC_AMD_COMMON_BLOCK_SPI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART
select SSE2