diff options
| author | Daniele Forsi <dforsi@gmail.com> | 2014-07-22 18:00:56 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-23 09:07:47 +0200 |
| commit | 53847a211bd78a9cbf838f63f155368c641f7cd5 (patch) | |
| tree | c0a72d2d52e7b70276aed0bcb15ebd8c794c8031 /src/soc | |
| parent | e34a6275eeebf324e921f8aa06e7c1c9fc0179f8 (diff) | |
src/.../Kconfig: various small fixes to texts
Fixed spelling and added empty lines to separate the help
from the text automatically added during make menuconfig.
Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6313
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/Kconfig | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index a93b487b87..a6a3a44cfa 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -148,7 +148,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE default 0x800 help The amount of anticipated stack usage from the data cache - during pre-ram rom stage execution. + during pre-RAM ROM stage execution. config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 312449ee67..cb4757bca3 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -78,7 +78,7 @@ config VGA_BIOS_ID default "8086,0f31" help This is the default PCI ID for the Bay Trail graphics - devices. This string names the vbios rom in cbfs. + devices. This string names the vbios ROM in cbfs. config INCLUDE_MICROCODE_IN_BUILD bool "Build in microcode patch" |