diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-10 01:26:07 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-02-11 00:50:14 +0000 |
| commit | 4f69ab729a9e0fe929728c5726e78f7769fe5a3a (patch) | |
| tree | ee2b29509b35eee4951087b024f5b38c364f2c1c /src/soc | |
| parent | ee2a3658727578721808620c526efa757f91aab0 (diff) | |
soc/amd*/smihandler: factor out and rename clear_all_smi_status
The old name was misleading, since it doesn't disable the generation of
SMIs, but clears the status registers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/smi.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/smi/smi_util.c | 11 | ||||
| -rw-r--r-- | src/soc/amd/picasso/smihandler.c | 13 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/smihandler.c | 13 |
4 files changed, 14 insertions, 24 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/smi.h b/src/soc/amd/common/block/include/amdblocks/smi.h index 31f9042ea8..25a1da7f34 100644 --- a/src/soc/amd/common/block/include/amdblocks/smi.h +++ b/src/soc/amd/common/block/include/amdblocks/smi.h @@ -47,5 +47,6 @@ void configure_scimap(const struct sci_source *sci); void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); +void clear_all_smi_status(void); #endif /* AMD_BLOCK_SMI_H */ diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index e3379f35fd..aa37dabe06 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -143,3 +143,14 @@ uint16_t pm_acpi_smi_cmd_port(void) { return pm_read16(PM_ACPI_SMI_CMD); } + +void clear_all_smi_status(void) +{ + smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); + smi_write32(SMI_EVENT_STATUS, smi_read32(SMI_EVENT_STATUS)); + smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0)); + smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1)); + smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2)); + smi_write32(SMI_REG_SMISTS3, smi_read32(SMI_REG_SMISTS3)); + smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); +} diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index d6c3ed0a41..5134358cb7 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -123,17 +123,6 @@ static void sb_apmc_smi_handler(void) mainboard_smi_apmc(cmd); } -static void disable_all_smi_status(void) -{ - smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); - smi_write32(SMI_EVENT_STATUS, smi_read32(SMI_EVENT_STATUS)); - smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0)); - smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1)); - smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2)); - smi_write32(SMI_REG_SMISTS3, smi_read32(SMI_REG_SMISTS3)); - smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); -} - static void sb_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; @@ -172,7 +161,7 @@ static void sb_slp_typ_handler(void) wbinvd(); - disable_all_smi_status(); + clear_all_smi_status(); /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ pci_ctrl = pm_read32(PM_PCI_CTRL); diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 45dd07d5af..e90bdb1b8c 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -118,17 +118,6 @@ static void sb_apmc_smi_handler(void) mainboard_smi_apmc(cmd); } -static void disable_all_smi_status(void) -{ - smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); - smi_write32(SMI_EVENT_STATUS, smi_read32(SMI_EVENT_STATUS)); - smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0)); - smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1)); - smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2)); - smi_write32(SMI_REG_SMISTS3, smi_read32(SMI_REG_SMISTS3)); - smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4)); -} - static void sb_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; @@ -167,7 +156,7 @@ static void sb_slp_typ_handler(void) wbinvd(); - disable_all_smi_status(); + clear_all_smi_status(); /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ pci_ctrl = pm_read32(PM_PCI_CTRL); |