diff options
| author | Justin TerAvest <teravest@chromium.org> | 2018-02-14 19:10:15 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-02-17 00:18:38 +0000 |
| commit | 3fe3f0409cd340112d62283bf79be9f106a6dff8 (patch) | |
| tree | 5df7ca98aa87050586b382be1e83920684a80ba1 /src/soc | |
| parent | 5b131e27c5d21d006950337cfd00e5fb35c7ed3b (diff) | |
soc/amd/stoneyridge: Normalize GPIO init
This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 14 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 14 |
3 files changed, 7 insertions, 23 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 709b4130a3..3eff5eb0dc 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -125,8 +125,6 @@ void bootblock_soc_init(void) post_code(0x37); do_agesawrapper(agesawrapper_amdinitreset, "amdinitreset"); - sb_program_gpio(); - post_code(0x38); /* APs will not exit amdinitearly */ do_agesawrapper(agesawrapper_amdinitearly, "amdinitearly"); diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f4d6b17a03..df78608cbb 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -340,19 +340,15 @@ void xhci_pm_write32(uint8_t reg, uint32_t value); uint32_t xhci_pm_read32(uint8_t reg); void bootblock_fch_early_init(void); /** - * @brief get table and table size to program GPIO - * - * @param size = pointer to variable where to return table size - * - * @return pointer to the desired table - */ -const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size); -/** * @brief program a particular set of GPIO * + * @param gpio_ptr = pointer to array of gpio configurations + * @param size = number of entries in array + * * @return none */ -void sb_program_gpio(void); +void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, + size_t size); /** * @brief Find the size of a particular wide IO * diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 735642f027..a14213fe61 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -155,15 +155,13 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) return irq_association; } -void sb_program_gpio(void) +void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr, + size_t size) { void *tmp_ptr; - const struct soc_amd_stoneyridge_gpio *gpio_ptr; - size_t size; uint8_t control, mux, index; printk(BIOS_SPEW, "GPIO programming stage %s\n", STR_GPIO_STAGE); - gpio_ptr = board_get_gpio(&size); for (index = 0; index < size; index++) { mux = gpio_ptr[index].function; control = gpio_ptr[index].control; @@ -181,14 +179,6 @@ void sb_program_gpio(void) printk(BIOS_SPEW, "End GPIO programming\n"); } -static void sb_program_gpio_ram(void *unused) -{ - sb_program_gpio(); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - sb_program_gpio_ram, NULL); - /** * @brief Find the size of a particular wide IO * |