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authorNico Huber <nico.h@gmx.de>2020-07-18 20:49:38 +0200
committerNico Huber <nico.h@gmx.de>2020-07-21 15:14:48 +0000
commit3c7888bf293ad6c5d879dd0ef1ddc1a6bad7470c (patch)
treeef13a75e5fe06712ec4fd19b3ca81fffa9b164fb /src/soc
parent767467dc67f4eb3c6b24e7cd6b548d0bdc0c2658 (diff)
libpayload/xhci: Try harder to read 32-bit caps at once
With commit 287cf6c7d1 (lp/drivers/usb: Work around QEMU XHCI register issue) we restructured our capability register accesses because the compiler used the wrong access size. While we do use only 32-bit types now, a compiler may still try to be clever and optimize things in unexpected ways. So we add an explicit read32() now. For instance for the 8-bit MaxPorts field, in the most significant bits of `capreg + 4`, our read + mask + shift ((cap)->hciparams1 & 0xff000000) >> 24 was turned into a single 8-bit read instruction by GCC on x86: 31: 0f b6 52 07 movzbl 0x7(%edx),%edx Change-Id: I76accd0ef718e70ca46807eb06a9177c3afd99f1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
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