aboutsummaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorStefan Reinauer <reinauer@chromium.org>2013-08-01 13:31:44 -0700
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-01-05 22:21:49 +0100
commit3a6550d989460f9449136814a8b1f6b051a6382d (patch)
treed60bdfd55ddcc5e45042c987d5216d9212784f60 /src/soc
parent83405a1241f4b8f516f687bd00f8ea981f7c7d87 (diff)
timestamps: Switch from tsc_t to uint64_t
Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c22
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c22
-rw-r--r--src/soc/intel/fsp_baytrail/romstage/romstage.c19
3 files changed, 15 insertions, 48 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index b69b532e31..ac5afabffd 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -44,20 +44,6 @@
#include <baytrail/smm.h>
#include <baytrail/spi.h>
-static inline uint64_t timestamp_get(void)
-{
- return rdtscll();
-}
-
-static inline tsc_t ts64_to_tsc(uint64_t ts)
-{
- tsc_t tsc = {
- .lo = ts,
- .hi = ts >> 32,
- };
- return tsc;
-}
-
/* The cache-as-ram assembly file calls romstage_main() after setting up
* cache-as-ram. romstage_main() will then call the mainboards's
* mainboard_romstage_entry() function. That function then calls
@@ -274,10 +260,10 @@ void romstage_common(struct romstage_params *params)
chromeos_init(prev_sleep_state);
/* Save timestamp information. */
- timestamp_init(ts64_to_tsc(params->ts.times[0]));
- timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
- timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2]));
- timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3]));
+ timestamp_init(params->ts.times[0]);
+ timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
+ timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
+ timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
}
void asmlinkage romstage_after_car(void)
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 4a5a47c35e..f234fda034 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -38,20 +38,6 @@
#include <broadwell/romstage.h>
#include <broadwell/spi.h>
-static inline uint64_t timestamp_get(void)
-{
- return rdtscll();
-}
-
-static inline tsc_t ts64_to_tsc(uint64_t ts)
-{
- tsc_t tsc = {
- .lo = ts,
- .hi = ts >> 32,
- };
- return tsc;
-}
-
static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
{
struct romstage_timestamps *rt = &rp->ts;
@@ -142,10 +128,10 @@ void romstage_common(struct romstage_params *params)
chromeos_init(params->power_state->prev_sleep_state);
/* Save timestamp information. */
- timestamp_init(ts64_to_tsc(params->ts.times[0]));
- timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
- timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2]));
- timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3]));
+ timestamp_init(params->ts.times[0]);
+ timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
+ timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
+ timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
}
void asmlinkage romstage_after_car(void)
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 2619c96f62..ad42e73b2b 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -221,10 +221,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
struct romstage_handoff *handoff;
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- tsc_t after_initram_time = rdtsc();
- tsc_t base_time;
- base_time.hi = 0;
- base_time.lo = 0;
+ uint64_t after_initram_time = timestamp_get();
#endif
post_code(0x4a);
@@ -244,9 +241,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
report_platform_info();
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- after_initram_time = rdtsc();
-#endif
post_code(0x4b);
late_mainboard_romstage_entry();
@@ -271,13 +265,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
-
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- timestamp_init(base_time);
- timestamp_reinit();
+ timestamp_init(get_initial_timestamp());
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE);
-#endif
post_code(0x4f);
@@ -285,3 +275,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
copy_and_run();
while (1);
}
+
+uint64_t get_initial_timestamp(void)
+{
+ return 0;
+}