soc/amd: factor out functionality to print last reset source

Change-Id: I5cec38dac7ea27aa316f5dd4f91ed84627a0f937
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

7 files changed, 63 insertions, 108 deletions

diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc
index c93e67d77b..8981231cff 100644
--- a/src/soc/amd/common/block/acpimmio/Makefile.inc
+++ b/src/soc/amd/common/block/acpimmio/Makefile.inc
@@ -10,4 +10,6 @@ postcar-y += biosram.c
 ramstage-y += biosram.c
 smm-y += biosram.c
 
+bootblock-y += print_reset_status.c
+
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO
diff --git a/src/soc/amd/common/block/acpimmio/print_reset_status.c b/src/soc/amd/common/block/acpimmio/print_reset_status.c
new file mode 100644
index 0000000000..3825753f84
--- /dev/null
+++ b/src/soc/amd/common/block/acpimmio/print_reset_status.c
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <amdblocks/acpimmio.h>
+
+static void print_num_status_bits(int num_bits, uint32_t status,
+				  const char *const bit_names[])
+{
+	int i;
+
+	if (!status)
+		return;
+
+	for (i = num_bits - 1; i >= 0; i--) {
+		if (status & (1 << i)) {
+			if (bit_names[i])
+				printk(BIOS_DEBUG, "%s ", bit_names[i]);
+			else
+				printk(BIOS_DEBUG, "BIT%d ", i);
+		}
+	}
+}
+
+void fch_print_pmxc0_status(void)
+{
+	/* PMxC0 S5/Reset Status shows the source of previous reset. */
+	uint32_t pmxc0_status = pm_read32(PM_RST_STATUS);
+
+	static const char *const pmxc0_status_bits[32] = {
+		[0] = "ThermalTrip",
+		[1] = "FourSecondPwrBtn",
+		[2] = "Shutdown",
+		[3] = "ThermalTripFromTemp",
+		[4] = "RemotePowerDownFromASF",
+		[5] = "ShutDownFan0",
+		[16] = "UserRst",
+		[17] = "SoftPciRst",
+		[18] = "DoInit",
+		[19] = "DoReset",
+		[20] = "DoFullReset",
+		[21] = "SleepReset",
+		[22] = "KbReset",
+		[23] = "LtReset",
+		[24] = "FailBootRst",
+		[25] = "WatchdogIssueReset",
+		[26] = "RemoteResetFromASF",
+		[27] = "SyncFlood",
+		[28] = "HangReset",
+		[29] = "EcWatchdogRst",
+	};
+
+	printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status);
+	print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, pmxc0_status_bits);
+	printk(BIOS_DEBUG, "\n");
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 0e42ee60c3..4fcaa9204a 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -20,6 +20,7 @@
 #define   SMBUS_ASF_IO_EN		(1 << 4)
 #define   CF9_IO_EN			(1 << 1)
 #define   LEGACY_IO_EN			(1 << 0)
+#define PM_RST_STATUS			0xc0
 
 /*
  * Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs
@@ -85,6 +86,9 @@ void pm_io_write8(uint8_t reg, uint8_t value);
 void pm_io_write16(uint8_t reg, uint16_t value);
 void pm_io_write32(uint8_t reg, uint32_t value);
 
+/* Print source of last reset */
+void fch_print_pmxc0_status(void);
+
 static inline uint8_t sm_pci_read8(uint8_t reg)
 {
 	return read8(acpimmio_sm_pci + reg);
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 13ef53fc56..a74e91f2bc 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -78,7 +78,6 @@
 #define   PM_ACPI_RTC_WAKE_EN		BIT(29)
 #define PM_RST_CTRL1			0xbe
 #define   SLPTYPE_CONTROL_EN		BIT(5)
-#define PM_RST_STATUS			0xc0
 #define PM_LPC_GATING			0xec
 #define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
 #define   PM_LPC_A20_EN			BIT(1)
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 3110deaa02..03c424ec6f 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -132,62 +132,10 @@ void fch_pre_init(void)
 		set_uart_config(CONFIG_UART_FOR_CONSOLE);
 }
 
-static void print_num_status_bits(int num_bits, uint32_t status,
-				  const char *const bit_names[])
-{
-	int i;
-
-	if (!status)
-		return;
-
-	for (i = num_bits - 1; i >= 0; i--) {
-		if (status & (1 << i)) {
-			if (bit_names[i])
-				printk(BIOS_DEBUG, "%s ", bit_names[i]);
-			else
-				printk(BIOS_DEBUG, "BIT%d ", i);
-		}
-	}
-}
-
-static void sb_print_pmxc0_status(void)
-{
-	/* PMxC0 S5/Reset Status shows the source of previous reset. */
-	uint32_t pmxc0_status = pm_read32(PM_RST_STATUS);
-
-	static const char *const pmxc0_status_bits[32] = {
-		[0] = "ThermalTrip",
-		[1] = "FourSecondPwrBtn",
-		[2] = "Shutdown",
-		[3] = "ThermalTripFromTemp",
-		[4] = "RemotePowerDownFromASF",
-		[5] = "ShutDownFan0",
-		[16] = "UserRst",
-		[17] = "SoftPciRst",
-		[18] = "DoInit",
-		[19] = "DoReset",
-		[20] = "DoFullReset",
-		[21] = "SleepReset",
-		[22] = "KbReset",
-		[23] = "LtReset",
-		[24] = "FailBootRst",
-		[25] = "WatchdogIssueReset",
-		[26] = "RemoteResetFromASF",
-		[27] = "SyncFlood",
-		[28] = "HangReset",
-		[29] = "EcWatchdogRst",
-	};
-
-	printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status);
-	print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status,
-			      pmxc0_status_bits);
-	printk(BIOS_DEBUG, "\n");
-}
-
 /* After console init */
 void fch_early_init(void)
 {
-	sb_print_pmxc0_status();
+	fch_print_pmxc0_status();
 	i2c_soc_early_init();
 
 	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index a4f43ec112..c627f7ec7c 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -72,7 +72,6 @@
 #define   PM_ACPI_RTC_WAKE_EN		BIT(29)
 #define PM_RST_CTRL1			0xbe
 #define   SLPTYPE_CONTROL_EN		BIT(5)
-#define PM_RST_STATUS			0xc0
 #define PM_PCIB_CFG			0xea
 #define   PM_GENINT_DISABLE		BIT(0)
 #define PM_LPC_GATING			0xec
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index ba23e90b58..4436e0ebf0 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -344,62 +344,10 @@ void bootblock_fch_early_init(void)
 	enable_aoac_devices();
 }
 
-static void print_num_status_bits(int num_bits, uint32_t status,
-				  const char *const bit_names[])
-{
-	int i;
-
-	if (!status)
-		return;
-
-	for (i = num_bits - 1; i >= 0; i--) {
-		if (status & (1 << i)) {
-			if (bit_names[i])
-				printk(BIOS_DEBUG, "%s ", bit_names[i]);
-			else
-				printk(BIOS_DEBUG, "BIT%d ", i);
-		}
-	}
-}
-
-static void sb_print_pmxc0_status(void)
-{
-	/* PMxC0 S5/Reset Status shows the source of previous reset. */
-	uint32_t pmxc0_status = pm_read32(PM_RST_STATUS);
-
-	static const char *const pmxc0_status_bits[32] = {
-		[0] = "ThermalTrip",
-		[1] = "FourSecondPwrBtn",
-		[2] = "Shutdown",
-		[3] = "ThermalTripFromTemp",
-		[4] = "RemotePowerDownFromASF",
-		[5] = "ShutDownFan0",
-		[16] = "UserRst",
-		[17] = "SoftPciRst",
-		[18] = "DoInit",
-		[19] = "DoReset",
-		[20] = "DoFullReset",
-		[21] = "SleepReset",
-		[22] = "KbReset",
-		[23] = "LtReset",
-		[24] = "FailBootRst",
-		[25] = "WatchdogIssueReset",
-		[26] = "RemoteResetFromASF",
-		[27] = "SyncFlood",
-		[28] = "HangReset",
-		[29] = "EcWatchdogRst",
-	};
-
-	printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status);
-	print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status,
-			      pmxc0_status_bits);
-	printk(BIOS_DEBUG, "\n");
-}
-
 /* After console init */
 void bootblock_fch_init(void)
 {
-	sb_print_pmxc0_status();
+	fch_print_pmxc0_status();
 }
 
 void sb_enable(struct device *dev)