diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-01-18 14:06:42 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:16:59 +0200 |
| commit | 35dc00f75b3345fda78df56fe29495eb5fdf5827 (patch) | |
| tree | 5045c8c1c5e11e2e5b784e366430454abb213f43 /src/soc | |
| parent | f059b241ad1ebd6b2084578b9284a19d018e8800 (diff) | |
broadwell: Preserve VbNv around cmos_init
To ensure that boot flags (legacy, usb, signed-only) are
properly restored from CMOS and used in the first boot after
a battery removal or RTC reset then the VbNv region needs to
be preserved around the cmos_init call.
When using vboot firmware selection and VbNv is stored in CMOS
then that region of CMOS will have been re-initialized by the
time we call cmos_init and reset CMOS if the chipset flag was
set indicating a problem.
BUG=chrome-os-partner:35240
BRANCH=broadwell
TEST=manual testing on samus:
1) boot in dev mode, enable dev_boot_legacy and ensure it works
2) on EC console pulse PCH_RTCRST_L low for a second
3) ensure first boot after RTC reset will still boot legacy mode
4) remove battery for a time
5) ensure first boot after battery is re-inserted will still
boot legacy mode
Change-Id: Ica256bbdcba6d4616957ff38e63914dd15f645c6
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 881c7841c95dec392a66eef38a7112c1f385fdfa
Original-Change-Id: I4c33f183ba4b301d68ae31c41fc6663f3be857b0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241529
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9495
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 6ebc758c46..9a4c65c8f3 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -49,6 +49,10 @@ #include <arch/acpigen.h> #include <cpu/cpu.h> +#if IS_ENABLED(CONFIG_CHROMEOS) +#include <vendorcode/google/chromeos/chromeos.h> +#endif + static void pch_enable_ioapic(struct device *dev) { u32 reg32; @@ -174,6 +178,25 @@ static void pch_power_options(device_t dev) enable_alt_smi(config->alt_gp_smi_en); } +#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS) +/* + * Preserve Vboot NV data when clearing CMOS as it will + * have been re-initialized already by Vboot firmware init. + */ +static void pch_cmos_init_preserve(int reset) +{ + uint8_t vbnv[CONFIG_VBNV_SIZE]; + + if (reset) + read_vbnv(vbnv); + + cmos_init(reset); + + if (reset) + save_vbnv(vbnv); +} +#endif + static void pch_rtc_init(struct device *dev) { u8 reg8; @@ -187,7 +210,11 @@ static void pch_rtc_init(struct device *dev) printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); } +#if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS) + pch_cmos_init_preserve(rtc_failed); +#else cmos_init(rtc_failed); +#endif } static const struct reg_script pch_misc_init_script[] = { |