diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-10-26 13:19:20 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-02 08:13:25 +0000 |
| commit | 3306f37fd60ddb19e78816327dc0655dbf39186e (patch) | |
| tree | 3da44350f39f599217c0d9276824a666f0df39d0 /src/soc | |
| parent | 35bcf5071ccf3c4a56445b172b64d2ce515a39e9 (diff) | |
lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()
Add DDR5 and LPDDR5 memory type checks while calculating bus width
extension (in bits).
Additionally, update all caller functions of
smbios_bus_width_to_spd_width() to pass `MemoryType` as argument.
Update `test_smbios_bus_width_to_spd_width()` to accommodate
different memory types.
Create new macro to fix incorrect bus width reporting
on platform with DDR5 and LPDDR5 memory.
With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit
primary bus width per Ch showed the Total width as:
Handle 0x000F, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0009
Error Information Handle: Not Provided
Total Width: 80 bits
Data Width: 64 bits
Size: 16 GB
...
BUG=b:194659789
Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`.
Change-Id: I79ec64c9d522a34cb44b3f575725571823048380
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/fsp/dmi.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/pi/amd_late_init.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/smbios.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index 61d43f7aae..223cce1577 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -54,8 +54,8 @@ static void transfer_memory_info(const TYPE17_DMI_INFO *dmi17, dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor); - dimm->bus_width = - smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth); + dimm->bus_width = smbios_bus_width_to_spd_width(dmi17->MemoryType, dmi17->TotalWidth, + dmi17->DataWidth); dimm->mod_id = dmi17->ManufacturerIdCode; diff --git a/src/soc/amd/common/pi/amd_late_init.c b/src/soc/amd/common/pi/amd_late_init.c index 25aaea37bf..3714404590 100644 --- a/src/soc/amd/common/pi/amd_late_init.c +++ b/src/soc/amd/common/pi/amd_late_init.c @@ -38,8 +38,8 @@ static void transfer_memory_info(TYPE17_DMI_INFO *dmi17, dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor); - dimm->bus_width = - smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth); + dimm->bus_width = smbios_bus_width_to_spd_width(dmi17->MemoryType, dmi17->TotalWidth, + dmi17->DataWidth); dimm->mod_id = dmi17->ManufacturerIdCode; diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index a2b4a0be0d..213be6578b 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -65,5 +65,5 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, if (ecc_support) total_width += EXTENSION_BUS_WIDTH_8BITS; - dimm->bus_width = smbios_bus_width_to_spd_width(total_width, data_width); + dimm->bus_width = smbios_bus_width_to_spd_width(ddr_type, total_width, data_width); } |