diff options
| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-04-01 18:36:11 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2022-04-04 17:49:17 +0000 |
| commit | 311ddf3b81b276553fb3a1973343b5ca31f85dbe (patch) | |
| tree | f87f5453c6b0fb58c614cbb0e249b7cb78ebc436 /src/soc | |
| parent | 9e78dd13577b577f96699710fefd965acda686e1 (diff) | |
soc/intel/alderlake: Add new CPU ID
Add new CPU ID 0x906A3 (L0 stepping).
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I280da46e5fdd3792df50556e2804b3bcb346eee3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63302
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/report_platform.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/mp_init.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 721355c06a..bdce2b7b84 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -25,6 +25,7 @@ static struct { } cpu_table[] = { { CPUID_ALDERLAKE_J0, "Alderlake J0 Platform" }, { CPUID_ALDERLAKE_K0, "Alderlake K0 Platform" }, + { CPUID_ALDERLAKE_L0, "Alderlake L0 Platform" }, { CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" }, { CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" }, { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 0305815750..823f23edfc 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -72,6 +72,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_L0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 }, |