soc/intel/skylake: Add USB Port Over Current (OC) Pin programming

Program USB Overcurrent pins as per board schematics definition.

BUG=none
BRANCH=none
TEST=Build and boot kunimitsu from USB device.

Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

3 files changed, 41 insertions, 11 deletions

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 2703224883..c64a8df589 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -90,6 +90,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 		params->PortUsb20Enable[i] =
 			config->usb2_ports[i].enable;
+		params->Usb2OverCurrentPin[i] =
+			config->usb2_ports[i].ocpin;
 		params->Usb2AfePetxiset[i] =
 			config->usb2_ports[i].pre_emp_bias;
 		params->Usb2AfeTxiset[i] =
@@ -102,6 +104,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 
 	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 		if (config->usb3_ports[i].tx_de_emp) {
 			params->Usb3HsioTxDeEmphEnable[i] = 1;
 			params->Usb3HsioTxDeEmph[i] =
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 582cdbf31d..f90f6bc096 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -121,6 +121,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 		params->PortUsb20Enable[i] =
 				config->usb2_ports[i].enable;
+		params->Usb2OverCurrentPin[i] =
+				config->usb2_ports[i].ocpin;
 		params->Usb2AfePetxiset[i] =
 				config->usb2_ports[i].pre_emp_bias;
 		params->Usb2AfeTxiset[i] =
@@ -133,6 +135,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
 		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+		params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 		if (config->usb3_ports[i].tx_de_emp) {
 			params->Usb3HsioTxDeEmphEnable[i] = 1;
 			params->Usb3HsioTxDeEmph[i] =
diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h
index a18e79ce66..77a94a8765 100644
--- a/src/soc/intel/skylake/include/soc/usb.h
+++ b/src/soc/intel/skylake/include/soc/usb.h
@@ -38,14 +38,25 @@
 
 struct usb2_port_config {
 	uint8_t enable;
+	uint8_t ocpin;
 	uint8_t tx_bias;
 	uint8_t tx_emp_enable;
 	uint8_t pre_emp_bias;
 	uint8_t pre_emp_bit;
 };
 
+/* USB Overcurrent pins definition */
+enum {
+	OC0,
+	OC1,
+	OC2,
+	OC3,
+	OC_SKIP = 8, /* Skip OC programming */
+};
+
 #define USB2_PORT_EMPTY { \
 	.enable        = 0, \
+	.ocpin         = OC_SKIP, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_EMP_OFF, \
 	.pre_emp_bias  = USB2_BIAS_0MV, \
@@ -62,8 +73,9 @@ struct usb2_port_config {
  */
 
 /* Max TX and Pre-emp settings */
-#define USB2_PORT_MAX { \
+#define USB2_PORT_MAX(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_56MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -71,8 +83,9 @@ struct usb2_port_config {
 }
 
 /* 11.5"-12" */
-#define USB2_PORT_LONG { \
+#define USB2_PORT_LONG(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_39MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -80,8 +93,9 @@ struct usb2_port_config {
 }
 
 /* 6"-11.5" */
-#define USB2_PORT_MID { \
+#define USB2_PORT_MID(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -89,8 +103,9 @@ struct usb2_port_config {
 }
 
 /* 3"-6" */
-#define USB2_PORT_SHORT { \
+#define USB2_PORT_SHORT(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_39MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_39MV, \
@@ -98,8 +113,9 @@ struct usb2_port_config {
 }
 
 /* Type-C Port, no BC1.2 charge detect module / MUX */
-#define USB2_PORT_TYPE_C { \
+#define USB2_PORT_TYPE_C(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -107,8 +123,9 @@ struct usb2_port_config {
 }
 
 /* Port with BC1.2 charge detect module / MUX */
-#define USB2_PORT_BC12_MUX { \
+#define USB2_PORT_BC12_MUX(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -116,8 +133,9 @@ struct usb2_port_config {
 }
 
 /* Internal Flex Cable, 3"-5" + cable + 2" card */
-#define USB2_PORT_FLEX { \
+#define USB2_PORT_FLEX(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -125,8 +143,9 @@ struct usb2_port_config {
 }
 
 /* Docking, 3"-9" */
-#define USB2_PORT_DOCKING_LONG { \
+#define USB2_PORT_DOCKING_LONG(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_0MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -134,8 +153,9 @@ struct usb2_port_config {
 }
 
 /* Docking, 3"-6" */
-#define USB2_PORT_DOCKING_SHORT { \
+#define USB2_PORT_DOCKING_SHORT(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_17MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_45MV, \
@@ -143,8 +163,9 @@ struct usb2_port_config {
 }
 
 /* 2:1 Detachable, 2"-4" on tablet + 2"-4" on base */
-#define USB2_PORT_DETACHABLE_TABLET { \
+#define USB2_PORT_DETACHABLE_TABLET(pin) { \
 	.enable        = 1, \
+	.ocpin         = pin, \
 	.tx_bias       = USB2_BIAS_56MV, \
 	.tx_emp_enable = USB2_PRE_EMP_ON, \
 	.pre_emp_bias  = USB2_BIAS_56MV, \
@@ -153,18 +174,21 @@ struct usb2_port_config {
 
 struct usb3_port_config {
 	uint8_t enable;
+	uint8_t ocpin;
 	uint8_t tx_de_emp;
 	uint8_t tx_downscale_amp;
 };
 
 #define USB3_PORT_EMPTY { \
 	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
 	.tx_de_emp        = 0x00, \
 	.tx_downscale_amp = 0x00, \
 }
 
-#define USB3_PORT_DEFAULT { \
+#define USB3_PORT_DEFAULT(pin) { \
 	.enable           = 1, \
+	.ocpin            = pin, \
 	.tx_de_emp        = 0x29, \
 	.tx_downscale_amp = 0x00, \
 }