diff options
| author | Julius Werner <jwerner@chromium.org> | 2016-04-06 12:50:40 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2016-04-07 20:46:38 +0200 |
| commit | 2b6db9738ef6d09a068b65ef472c2d54f99abc37 (patch) | |
| tree | ab43af5cac7b2d75fbb65705b2c43d1db0e45eca /src/soc | |
| parent | 2268e0dc15d076c61792b97e954cad3f7c5f8c00 (diff) | |
edid: Make framebuffer row alignment configurable
Our EDID code had always been aligning the framebuffer's
bytes_per_line (and x_resolution dependent on that) to 64. It turns out
that this is a controller-dependent parameter that seems to only really
be necessary for Intel chipsets, and commit 6911219cc (edid: Add helper
function to calculate bits-per-pixel dependent values) probably actually
broke this for some other controllers by applying the alignment too
widely.
This patch makes it explicitly configurable and depends the default on
ARCH_X86 (which seems to be the simplest and least intrusive way to make
it fit most cases for now... boards where this doesn't apply can still
override it manually by calling edid_set_framebuffer_bits_per_pixel()
again).
Change-Id: I1c565a72826fc5ddfbb1ae4a5db5e9063b761455
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14267
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/nvidia/tegra124/display.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/dc.c | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/dc.c | 2 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/display.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 74202bad23..bb96831514 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -334,6 +334,6 @@ void display_startup(device_t dev) edid.mode.va = config->yres; edid.mode.ha = config->xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel); + config->framebuffer_bits_per_pixel, 0); set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); } diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c index 562061a1d3..3ae25bc2f5 100644 --- a/src/soc/nvidia/tegra132/dc.c +++ b/src/soc/nvidia/tegra132/dc.c @@ -230,7 +230,7 @@ void pass_mode_info_to_payload( edid.mode.va = config->display_yres; edid.mode.ha = config->display_xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel); + config->framebuffer_bits_per_pixel, 0); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 72f1bcb3fa..88e599defd 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -230,7 +230,7 @@ void pass_mode_info_to_payload( edid.mode.va = config->display_yres; edid.mode.ha = config->display_xres; edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel); + config->framebuffer_bits_per_pixel, 0); printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " " x_res x y_res: %d x %d, size: %d\n", diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 66b2edc5b8..306baad3b6 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -95,7 +95,7 @@ void rk_display_init(device_t dev, u32 lcdbase, } edid_set_framebuffer_bits_per_pixel(&edid, - conf->framebuffer_bits_per_pixel); + conf->framebuffer_bits_per_pixel, 0); rkvop_mode_set(conf->vop_id, &edid, detected_mode); rkvop_enable(conf->vop_id, lcdbase, &edid); |