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authorSubrata Banik <subrata.banik@intel.com>2017-08-29 17:25:46 +0530
committerSubrata Banik <subrata.banik@intel.com>2017-08-30 15:45:14 +0000
commit2678cd693a766f722e67c7d650a95e1d4a9af404 (patch)
tree5726ceee236bc4baddaf5e170133ea35cb18d613 /src/soc
parentf10c8f9cf3930db624955f04cb6434d69e16030e (diff)
soc/intel/cannonlake: Add PrmrrSize and C6DRAM config
This patch ensures coreboot can set PRMRR size and C6DRAM enable FSP-M UPDs. Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/chip.h8
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c2
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 48305fe642..0ed41fc824 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -186,6 +186,14 @@ struct soc_intel_cannonlake_config {
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;
+ /* Enable C6 DRAM */
+ uint8_t enable_c6dram;
+ /*
+ * PRMRR size setting with below options
+ * 0x00100000 - 1MiB
+ * 0x02000000 - 32MiB and beyond
+ */
+ uint32_t PrmrrSize;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 17c31910e9..5fa39ca933 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -82,6 +82,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
mask |= (1 << i);
}
m_cfg->PcieRpEnableMask = mask;
+ m_cfg->PrmrrSize = config->PrmrrSize;
+ m_cfg->EnableC6Dram = config->enable_c6dram;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)