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authorphilipchen <philipchen@google.com>2017-04-27 18:25:11 -0700
committerJulius Werner <jwerner@chromium.org>2017-05-03 21:45:56 +0200
commit21b08522c27f2e70a081f4634dc0404c7eeb94f9 (patch)
tree99c1c83eb3a875567b37f0738781d02ee983f94b /src/soc
parentecf3489df8e01003495a5943f4af2700e6c20939 (diff)
google/gru: skip usbphy1 setup for Scarlet
Board Scarlet doesn't use usbphy1. BUG=b:37685249 TEST=boot Scarlet, check the firmware log, and confirm no errors about USB1 Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/19489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/rockchip/rk3399/include/soc/grf.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h
index c1fd690e78..8e120071a0 100644
--- a/src/soc/rockchip/rk3399/include/soc/grf.h
+++ b/src/soc/rockchip/rk3399/include/soc/grf.h
@@ -71,10 +71,8 @@ struct rk3399_grf_regs {
u32 reserved10[0xc9];
u32 hsicphy_con0;
u32 reserved11[3];
- u32 usbphy0_ctrl[26];
- u32 reserved12[6];
- u32 usbphy1_ctrl[26];
- u32 reserved13[0x72f];
+ u32 usbphy_ctrl[2][26 + 6]; /* 26 PHY regs, 6 reserved padding regs */
+ u32 reserved13[0x729];
u32 soc_con9;
u32 reserved14[0x0a];
u32 soc_con20;