diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-13 00:54:32 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-14 02:24:39 +0000 |
| commit | 1b46e76df9ef0a4b38d782732ee914ab70667bfa (patch) | |
| tree | 83b3471f79037cc7376e2817ddd2905922d4f7eb /src/soc | |
| parent | e3f7ef22864402e72e1fa6c1df3bc79199c40bdc (diff) | |
include/cpu/x86/msr: introduce IA32_MC_*(x) macros
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4
and added to the IA32_MC0_* define to get the MSR number. Add a macro
that already does this calculation to avoid open coding this repeatedly.
Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/mca.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 4 |
2 files changed, 9 insertions, 10 deletions
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 920ee7d515..0773101a29 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -119,8 +119,7 @@ static void build_bert_mca_error(struct mca_bank_status *mci) ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); if (!ctx) goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, - IA32_MC0_CTL + (mci->bank * 4), 4); + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, @@ -152,13 +151,13 @@ static void mca_print_error(unsigned int bank) printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, mca_bank_name[bank]); - msr = rdmsr(IA32_MC0_STATUS + (bank * 4)); + msr = rdmsr(IA32_MC_STATUS(bank)); printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_ADDR + (bank * 4)); + msr = rdmsr(IA32_MC_ADDR(bank)); printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_MISC + (bank * 4)); + msr = rdmsr(IA32_MC_MISC(bank)); printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_CTL + (bank * 4)); + msr = rdmsr(IA32_MC_CTL(bank)); printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); msr = rdmsr(MC0_CTL_MASK + bank); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); @@ -177,7 +176,7 @@ static void mca_check_all_banks(void) continue; mci.bank = i; - mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); + mci.sts = rdmsr(IA32_MC_STATUS(i)); if (mci.sts.hi || mci.sts.lo) { mca_print_error(i); @@ -194,7 +193,7 @@ static void mca_clear_errors(void) /* Zero all machine check error status registers */ for (unsigned int i = 0 ; i < num_banks ; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); } void check_mca(void) diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 81e42aeda5..9e95b0f9f4 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -348,9 +348,9 @@ void mca_configure(void) for (i = 0; i < num_banks; i++) { /* Clear the machine check status */ - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); /* Initialize machine checks */ - wrmsr(IA32_MC0_CTL + i * 4, + wrmsr(IA32_MC_CTL(i), (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } |