diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-17 02:48:48 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-18 14:05:25 +0000 |
| commit | 19f4c39cfe106fe11a9abb3fe80f41f3917db316 (patch) | |
| tree | 76f31f74e4d43fd23704dd424cd1df375a689d83 /src/soc | |
| parent | 68143e88a8d66d4a3ba09c220e03dd3d7471687d (diff) | |
soc/amd/mendocino/agesa_acpi: use acpi_align_current to align IVRS&ALIB
This changes the alignment of the IVRS table from 8 bytes to 16 bytes
and aligns the ALIB table to a 16 byte boundary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b48a7cbed84551e7651992589c38eac54f27d1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/mendocino/agesa_acpi.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/mendocino/agesa_acpi.c b/src/soc/amd/mendocino/agesa_acpi.c index e0ca9ac926..7e85b13b87 100644 --- a/src/soc/amd/mendocino/agesa_acpi.c +++ b/src/soc/amd/mendocino/agesa_acpi.c @@ -15,10 +15,11 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current acpi_ivrs_t *ivrs; /* add ALIB SSDT from HOB */ + current = acpi_align_current(current); current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); /* IVRS */ - current = ALIGN_UP(current, 8); + current = acpi_align_current(current); ivrs = (acpi_ivrs_t *)current; acpi_create_ivrs(ivrs, acpi_fill_ivrs); current += ivrs->header.length; |