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authorMario Scheithauer <mario.scheithauer@siemens.com>2023-06-15 14:28:47 +0200
committerJakub Czapiga <jacz@semihalf.com>2023-06-19 11:09:36 +0000
commit16d1eb68d2e8c72a9ce1bca59cde21cd58452e66 (patch)
tree4cbdcd59bb341f1529b8d02f959f94fe41d32fd9 /src/soc
parentfeafddba8ed6961237e39debf2361f20a1bcf635 (diff)
soc/intel/apollolake: Switch to snake case for ModPhyIfValue
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/apollolake/chip.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index e3bfa1e273..a29ba3b19f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -612,7 +612,7 @@ static void glk_fsp_silicon_init_params_cb(
/*
* Options to change USB3 ModPhy setting for Integrated Filter value.
*/
- silconfig->ModPhyIfValue = cfg->ModPhyIfValue;
+ silconfig->ModPhyIfValue = cfg->mod_phy_if_value;
/*
* Options to bump USB3 LDO voltage with 40mv.
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index c1bc0209dc..26e4478da2 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -190,7 +190,7 @@ struct soc_intel_apollolake_config {
* value. Default is 0 to not changing default IF value (0x12). Set
* value with the range from 0x01 to 0xff to change IF value.
*/
- uint8_t ModPhyIfValue;
+ uint8_t mod_phy_if_value;
/* Options to bump USB3 LDO voltage. Default is FALSE to not increasing
* LDO voltage. Set TRUE to increase LDO voltage with 40mV.