diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-04-07 07:16:48 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-07 12:53:19 +0000 |
| commit | 11cac784ff788b4f0495758d7f5992e457ea552c (patch) | |
| tree | 15439643f00444d5b3a3d9415475f208faec0ba4 /src/soc | |
| parent | 0310d34c2f682b00431a052e770ad44656d1d6f6 (diff) | |
Replace some ENV_ROMSTAGE with ENV_RAMINIT
With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.
Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/pi/agesawrapper.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/pi/def_callouts.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/BiosCallOuts.c | 2 | ||||
| -rw-r--r-- | src/soc/cavium/cn81xx/sdram.c | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/emi.c | 2 | ||||
| -rw-r--r-- | src/soc/sifive/fu540/clock.c | 4 |
6 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c index c5e6cac465..40858553df 100644 --- a/src/soc/amd/common/pi/agesawrapper.c +++ b/src/soc/amd/common/pi/agesawrapper.c @@ -68,7 +68,7 @@ static AGESA_STATUS amd_create_struct(AMD_INTERFACE_PARAMS *aip, aip->NewStructPtr = buf; aip->NewStructSize = len; } else { - if (ENV_ROMSTAGE) + if (ENV_RAMINIT) aip->AllocationMethod = PreMemHeap; if (ENV_RAMSTAGE) aip->AllocationMethod = PostMemDram; @@ -412,7 +412,7 @@ AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) StdHeader = aip->NewStructPtr; StdHeader->Func = func; - if (ENV_ROMSTAGE) + if (ENV_RAMINIT) status = romstage_dispatch(StdHeader); if (ENV_RAMSTAGE) status = ramstage_dispatch(StdHeader); diff --git a/src/soc/amd/common/pi/def_callouts.c b/src/soc/amd/common/pi/def_callouts.c index 414de6f8ce..223abe3169 100644 --- a/src/soc/amd/common/pi/def_callouts.c +++ b/src/soc/amd/common/pi/def_callouts.c @@ -23,7 +23,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = { #else const BIOS_CALLOUT_STRUCT BiosCallouts[] = { /* Required callouts */ -#if ENV_ROMSTAGE +#if ENV_RAMINIT { AGESA_HALT_THIS_AP, agesa_HaltThisAp }, #endif { AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index ba0f0ee950..b94f3a65b9 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -86,7 +86,7 @@ AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr) DEVTREE_CONST struct soc_amd_stoneyridge_config *conf; AGESA_READ_SPD_PARAMS *info = ConfigPtr; - if (!ENV_ROMSTAGE) + if (!ENV_RAMINIT) return AGESA_UNSUPPORTED; dev = pcidev_path_on_root(DCT_DEVFN); diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c index 080adc093c..cdfa0f75fd 100644 --- a/src/soc/cavium/cn81xx/sdram.c +++ b/src/soc/cavium/cn81xx/sdram.c @@ -29,7 +29,7 @@ size_t sdram_size_mb(void) #define BDK_RNM_CTL_STATUS 0 #define BDK_RNM_RANDOM 0x100000 -#if ENV_ROMSTAGE +#if ENV_RAMINIT /* Enable RNG for DRAM init */ static void rnm_init(void) { diff --git a/src/soc/mediatek/mt8186/emi.c b/src/soc/mediatek/mt8186/emi.c index 6e2544185e..4f300da793 100644 --- a/src/soc/mediatek/mt8186/emi.c +++ b/src/soc/mediatek/mt8186/emi.c @@ -15,7 +15,7 @@ size_t sdram_size(void) const struct mem_chip_info *mc; size_t size = 0; - if (ENV_ROMSTAGE) { + if (ENV_RAMINIT) { size = mtk_dram_size(); printk(BIOS_INFO, "dram size (romstage): %#lx\n", size); return size; diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 977f938eb4..a8baddef9a 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -56,7 +56,7 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI; #define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5) /* Clock initialization should only be done in romstage. */ -#if ENV_ROMSTAGE +#if ENV_RAMINIT struct pll_settings { unsigned int divr:6; unsigned int divf:9; @@ -247,7 +247,7 @@ void clock_init(void) asm volatile ("fence"); } -#endif /* ENV_ROMSTAGE */ +#endif /* ENV_RAMINIT */ /* Get the core clock's frequency, in KHz */ int clock_get_coreclk_khz(void) |