diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-06-15 16:33:29 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-06-16 16:38:25 +0000 |
| commit | 117823e76fbbea0252b5874746b6bd1aa7609593 (patch) | |
| tree | d5b487fcad912800e65e643fde41bbd3914cc4c9 /src/soc | |
| parent | 3b46333b39701ac2fdbbeba8d863449904f12f7a (diff) | |
soc/amd/cezanne: factor out AOAC offset defines
Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9dfddb0d4f32a542fa652ff8c14e932c224f247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/aoac.c | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/aoac_defs.h | 21 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 14 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/uart.c | 1 |
4 files changed, 23 insertions, 14 deletions
diff --git a/src/soc/amd/cezanne/aoac.c b/src/soc/amd/cezanne/aoac.c index 9c58bb5442..c313a55b5f 100644 --- a/src/soc/amd/cezanne/aoac.c +++ b/src/soc/amd/cezanne/aoac.c @@ -3,6 +3,7 @@ #include <stdint.h> #include <amdblocks/acpimmio.h> #include <amdblocks/aoac.h> +#include <soc/aoac_defs.h> #include <soc/southbridge.h> #include <delay.h> diff --git a/src/soc/amd/cezanne/include/soc/aoac_defs.h b/src/soc/amd/cezanne/include/soc/aoac_defs.h new file mode 100644 index 0000000000..5309cb08b8 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/aoac_defs.h @@ -0,0 +1,21 @@ + +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_AOAC_DEFS_H +#define AMD_CEZANNE_AOAC_DEFS_H + +/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_I2C4 9 +#define FCH_AOAC_DEV_I2C5 10 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_ESPI 27 +#define FCH_AOAC_DEV_EMMC 28 + +#endif /* AMD_CEZANNE_AOAC_DEFS_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index f90964bd47..0ed5f33f22 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -105,20 +105,6 @@ #define I2C_PAD_CTRL_SPARE0 BIT(17) #define I2C_PAD_CTRL_SPARE1 BIT(18) -/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ -#define FCH_AOAC_DEV_CLK_GEN 0 -#define FCH_AOAC_DEV_I2C0 5 -#define FCH_AOAC_DEV_I2C1 6 -#define FCH_AOAC_DEV_I2C2 7 -#define FCH_AOAC_DEV_I2C3 8 -#define FCH_AOAC_DEV_I2C4 9 -#define FCH_AOAC_DEV_I2C5 10 -#define FCH_AOAC_DEV_UART0 11 -#define FCH_AOAC_DEV_UART1 12 -#define FCH_AOAC_DEV_AMBA 17 -#define FCH_AOAC_DEV_ESPI 27 -#define FCH_AOAC_DEV_EMMC 28 - void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c index 6c82f1a948..212f365bab 100644 --- a/src/soc/amd/cezanne/uart.c +++ b/src/soc/amd/cezanne/uart.c @@ -7,6 +7,7 @@ #include <console/console.h> #include <device/device.h> #include <device/mmio.h> +#include <soc/aoac_defs.h> #include <soc/gpio.h> #include <soc/southbridge.h> #include <soc/uart.h> |