diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-18 10:29:06 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-27 22:23:05 +0200 |
| commit | 0e90dae584c506b06e7bf3d89064a64db04132bb (patch) | |
| tree | 83876d4f6e39e432789c0bcdb6384068bdcd566b /src/soc | |
| parent | 40772a0b5afc7d82a213b005905e2d9e71a6328e (diff) | |
Move TPM code out of chromeos
This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.
Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 13 |
3 files changed, 12 insertions, 27 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index bfc86785a3..a32db02df5 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -33,6 +33,7 @@ #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> +#include <tpm.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -211,14 +212,6 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) return prev_sleep_state; } -static inline void chromeos_init(int prev_sleep_state) -{ -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */ - init_chromeos(prev_sleep_state == 3 ? 2 : 0); -#endif -} - /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -250,7 +243,9 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(prev_sleep_state); + if (CONFIG_LPC_TPM) { + init_tpm(prev_sleep_state == 3); + } } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 9c8bbc40ce..5e5b8be196 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -43,6 +43,7 @@ #include <soc/romstage.h> #include <soc/smm.h> #include <soc/spi.h> +#include <tpm.h> /* The cache-as-ram assembly file calls romstage_main() after setting up * cache-as-ram. romstage_main() will then call the mainboards's @@ -211,14 +212,6 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) return prev_sleep_state; } -static inline void chromeos_init(int prev_sleep_state) -{ -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */ - init_chromeos(prev_sleep_state == 3 ? 2 : 0); -#endif -} - /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -250,7 +243,9 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(prev_sleep_state); + if (CONFIG_LPC_TPM) { + init_tpm(prev_sleep_state == 3); + } } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 50d5b24405..e950b1ec6f 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -29,6 +29,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> +#include <tpm.h> #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> @@ -89,14 +90,6 @@ void * asmlinkage romstage_main(unsigned long bist, return setup_stack_and_mttrs(); } -static inline void chromeos_init(int prev_sleep_state) -{ -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */ - init_chromeos(prev_sleep_state == SLEEP_STATE_S3 ? 2 : 0); -#endif -} - /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -132,7 +125,9 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(params->power_state->prev_sleep_state); +#if CONFIG_LPC_TPM + init_tpm(prev_sleep_state == SLEEP_STATE_S3); +#endif } void asmlinkage romstage_after_car(void) |