diff options
| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2016-08-29 16:24:24 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-08-31 19:23:15 +0200 |
| commit | 07215aaf71cd617e9929ebfbba733954d6b0aa74 (patch) | |
| tree | ec9752d12f8b8b461943180eeccff5a1bcfcd09f /src/soc | |
| parent | 4dfe13081922454e97e6b0f8d6532cd97c635b60 (diff) | |
soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3
Update FSP Header files to provide UPD for periodic training
disable. This is for the SIC 1.1.3/150_11 FSP release.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=built coreboot image with new headers for reef
Change-Id: I2ba11aa3d2d664c1d34e39c4c8144fb1c4f2149a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16352
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index bb53497a43..88d4c42017 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -595,28 +595,28 @@ struct FSP_M_CONFIG { **/ uint8_t RecoverDump; -/** Offset 0x013A - Memory Region 0 Buffer Size +/** Offset 0x013A - Memory Region 0 Buffer WrapAround + Memory Region 0 Buffer WrapAround. 0-n0-wrap, 1-warp(Default). +**/ + uint8_t Msc0Wrap; + +/** Offset 0x013B - Memory Region 1 Buffer WrapAround + Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + uint8_t Msc1Wrap; + +/** Offset 0x013C - Memory Region 0 Buffer Size Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ uint32_t Msc0Size; -/** Offset 0x013E - Memory Region 0 Buffer WrapAround - Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - uint8_t Msc0Wrap; - -/** Offset 0x013F - Memory Region 1 Buffer Size +/** Offset 0x0140 - Memory Region 1 Buffer Size Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, 6-512MB, 7-1GB. **/ uint32_t Msc1Size; -/** Offset 0x0143 - Memory Region 1 Buffer WrapAround - Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). -**/ - uint8_t Msc1Wrap; - /** Offset 0x0144 - PTI Mode PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. **/ @@ -648,9 +648,15 @@ struct FSP_M_CONFIG { **/ uint8_t SwTraceEn; -/** Offset 0x014A +/** Offset 0x014A - Periodic Retraining Disable + Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t PeriodicRetrainingDisable; + +/** Offset 0x014B **/ - uint8_t ReservedFspmUpd[6]; + uint8_t ReservedFspmUpd[5]; } __attribute__((packed)); /** Fsp M Test Configuration |